MC56F8122 Datasheet PDF - Motorola

www.Datasheet-PDF.com

MC56F8122
Motorola

Part Number MC56F8122
Description (MC56F8122 / MC56F8322) 16-bit Hybrid Controllers
Page 30 Pages


MC56F8122 datasheet pdf
Download PDF
MC56F8122 pdf
View PDF for Mobile

No Preview Available !

56F8322/56F8122
Data Sheet
Preliminary Technical Data
56F8300
16-bit Hybrid Controllers
MC56F8322
Rev. 10.0
10/2004
freescale.com



No Preview Available !

Version History
Rev 1.0
Rev 2.0
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Rev 9.0
Rev. 10.0
Document Revision History
Description of Change
Pre-Release version, Alpha customers only
Initial Public Release
Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additional
grammar issues
Added Package Pins to GPIO table in Section 8. Clarification of TRST usage in this device.
Replacing TBD Typical Min with values in Table 10-17. Editing grammar, spelling,
consistency of language throughout family. Updated values in Regulator Parameters,
Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI Timing,
Table 10-18, ADC Parameters, Table 10-24, and IO Loading Coefficients at 10MHz,
Table 10-25
Updated values in Power-On Reset Low Voltage Table 10-6.
Added Section 4.8 , added addition text to Section 6.9 on POR reset, added the word
“access” to FM Error Interrupt in Table 4-3, removed min and max numbers; only
documenting Typ. numbers for LVI in Table 10-6.
Updated numbers in Table 10-7 and Table 10-8 with more recent data, Corrected typo in
Table 10-3 in Pd characteristics
Replace any reference to Flash Interface Unit with Flash Memory Module; corrected typo on
page 1 for ADC channel; changed example in Section 2.2 ; added note on VREFHand
VREFLO in Table 2-2 and Table 11-1; corrected typo FIVAL1 and FIVAH1 in Table 4-12;
removed unneccessary notes in Table 10-12; corrected temperature range in Table 10-14;
added ADC calibration information to Table 10-24 and new graphs in Figure 10-20.
Clarification to Table 10-23, corrected Digital Input Current Low (pull-up enabled) numbers in
Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1.
Added 56F8122 information; edited to indicate differences in 56F8322 and 56F8122.
Reformatted to reflect Freescale look and feel. Updated Temperature Sensor and ADC
tables, then updated balance of electrical tables for consistency throughout family. Clarified
I/O power description in Table 2-2, added note to Table 10-7 and clarified Section 12.3.
Please see http://www.freescale.com for the most current Data Sheet revision.
56F8322 Techncial Data, Rev. 10.0
2 Freescale Semiconductor
Preliminary



No Preview Available !

56F8322/56F8122 General Description
Note: Features in italics are NOT available in the 56F8122 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 32KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• One 6-channel PWM module
• Two 3-channel 12-bit ADCs
• Temperature Sensor
• One Quadrature Decoder
• FlexCAN module
• Up to two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Two general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 21 GPIO lines
• 48-pin LQFP Package
6 PWM Outputs
Fault Inputs
PWMA or
SPI1 or
GPIOA
RESET
4
VCAP VDD
24
VSS
4
VDDA VSSA
Program Controller
and Hardware
Looping Unit
JTAG/
EOnCE
Port
Digital Reg Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
3 AD0
3 AD1
3 VREF
Memory
Program Memory
16K x 16 Flash
2K x 16 RAM
XDB2
XAB1
XAB2
TEMP_SENSE
4K x 16 Boot
Flash
PAB
PDB
4
Quadrature
Decoder 0 or
Quad
Data Memory
4K x 16 Flash
4K x 16 RAM
CDBR
CDBW
Timer A or
GPIO B
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
IPBus Bridge (IPBB)
Quad Timer C
2 or SCI0
or GPIOC Decoding
Peripheral
Device Selects
RW
Control
2 FlexCAN or Peripherals
GPIOC
IPWDB IPRDB
Clock
resets
PLL
SPI0 or
SCI1 or
GPIOB
4
COP/
Interrupt
Watchdog Controller
IRQA
System P
Integration
O
R
Module
Clock
Generator*
O
S
C
XTAL or GPIOC
EXTAL or GPIOC
*Includes On-Chip
Relaxation Oscillator
56F8322/56F8122 Block Diagram
Freescale Semiconductor
Preliminary
56F8322 Technical Data, Rev. 10.0
3



No Preview Available !

Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . 5
1.1. 56F8322/56F8122 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . 8
1.4. Architecture Block Diagram . . . . . . . . . . . . . 9
1.5. Product Documentation . . . . . . . . . . . . . . . 13
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . 13
Part 2: Signal/Connection Descriptions . . 14
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 17
Part 3: On-Chip Clock Synthesis (OCCS) . 26
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2. External Clock Operation . . . . . . . . . . . . . . 26
3.3. Use of On-Chip Relaxation Oscillator . . . . . 28
3.4. Internal Clock Operation . . . . . . . . . . . . . . . 28
3.5. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Part 4: Memory Map . . . . . . . . . . . . . . . . . . 30
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 30
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 31
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 34
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 36
4.7. Peripheral Memory Mapped Registers . . . . 36
4.8. Factory-Programmed Memory . . . . . . . . . . 52
Part 5: Interrupt Controller (ITCN) . . . . . . . 52
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3. Functional Description . . . . . . . . . . . . . . . . 52
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 54
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 54
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 55
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Part 6: System Integration Module (SIM) . . 77
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 78
6.4. Operating Mode Register . . . . . . . . . . . . . . 79
6.5. Register Descriptions . . . . . . . . . . . . . . . . . 79
6.6. Clock Generation Overview . . . . . . . . . . . . 91
6.7. Power-Down Modes . . . . . . . . . . . . . . . . . . 91
6.8. Stop and Wait Mode Disable Function . . . . 92
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Part 7: Security Features . . . . . . . . . . . . . . 93
7.1. Operation with Security Enabled . . . . . . . . . 93
7.2. Flash Access Blocking Mechanisms . . . . . . 93
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . 96
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . .96
8.3. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . .98
Part 9: Joint Test Action Group (JTAG) . . . 98
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . .98
Part 10: Specifications . . . . . . . . . . . . . . . . 99
10.1. General Characteristics . . . . . . . . . . . . . . .99
10.2. DC Electrical Characteristics . . . . . . . . . .103
10.3. AC Electrical Characteristics . . . . . . . . . .107
10.4. Flash Memory Characteristics . . . . . . . . .108
10.5. External Clock Operation Timing . . . . . . .109
10.6. Phase Locked Loop Timing . . . . . . . . . . .110
10.7. Oscillator Parameters . . . . . . . . . . . . . . . .110
10.8. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . .113
10.9. Serial Peripheral Interface (SPI) Timing . .115
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . .118
10.11. Quadrature Decoder Timing . . . . . . . . . .118
10.12. Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . .119
10.13. Controller Area Network (CAN) Timing .120
10.14. JTAG Timing . . . . . . . . . . . . . . . . . . . . . .120
10.15. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . .122
10.16. Equivalent Circuit for ADC Inputs . . . . . .125
10.17. Power Consumption . . . . . . . . . . . . . . . .125
Part 11: Packaging . . . . . . . . . . . . . . . . . . 127
11.1. 56F8322 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . .127
11.2. 56F8122 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . .129
Part 12: Design Considerations . . . . . . . . 132
12.1. Thermal Design Considerations . . . . . . . .132
12.2. Electrical Design Considerations . . . . . . .133
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . .134
Part 13: Ordering Information . . . . . . . . . 135
56F8322 Techncial Data, Rev. 10.0
4 Freescale Semiconductor
Preliminary



MC56F8122 datasheet pdf
Download PDF
MC56F8122 pdf
View PDF for Mobile


Related : Start with MC56F812 Part Numbers by
MC56F8122 (MC56F8122 / MC56F8322) 16-bit Hybrid Controllers MC56F8122
Motorola
MC56F8122 pdf
MC56F8123 (MC56F8123 / MC56F8323) 16-bit Hybrid Controllers MC56F8123
Motorola
MC56F8123 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact