MC56F8014 Datasheet PDF - Freescale Semiconductor

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MC56F8014
Freescale Semiconductor

Part Number MC56F8014
Description 16-bit Digital Signal Controllers
Page 30 Pages


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56F8014
Data Sheet
Preliminary Technical Data
56F8000
16-bit Digital Signal Controllers
MC56F8014
Rev. 3
9/2005
freescale.com



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Version History
Rev 0
Rev 1
Rev 2
Rev 3
Document Revision History
Description of Change
Initial release
Updates to Part 10, Specifications,
Table 10-1, added maximum clamp current , per pin
Table 10-11, clarified variation over temperature table and graph
Table 10-15, added LIN slave timing
Added alternate pins to Figure 11-1 and Table 11-1.
Corrected bit selects in Timer Channel 3 Input (TC3_INP) bit 9 , Section 6.3.1.7, clarified
Section 1.4.1, and simplified notes in Table 10-9,
Please see http://www.freescale.com for the most current Data Sheet revision.
56F8014 Technical Data, Rev. 3
2
Freescale Semiconductor
Preliminary



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56F8014 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 16KB Program Flash
• 4KB Unified Data/Program RAM
• One 5-channel PWM module
• Two 4-channel 12-bit ADCs
• One Serial Communication Interface (SCI) with LIN
slave functionality
• One Serial Peripheral Interface (SPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I2C) Port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset and Low-Voltage Interrupt
Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package
5 PWM Outputs
4 AD0 ADC
or
GPIOC
4 AD1
RESET
4
VCAP
VDD
VSS_IO VDDA
2
VSSA
PWM
or Timer Port
or GPIOA
JTAG/EOnCE
Port or
GPIOD
Digital Reg Analog Reg
16-Bit
56800E Core
Low-Voltage
Supervisor
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
Memory
Program Memory
8K x 16 Flash
Unified Data /
Program RAM
4KB
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
2 Timer or
GPIOB
IPBus Bridge (IPBB)
SPI or I2C
or Timer
or GPIOB
4
SCI
or I2C
or GPIOB
2
COP/
Watchdog
Interrupt
Controller
System
Integration
Module
P
O
R
Clock
Generator*
O
S
C
*Includes On-Chip
Relaxation Oscillator
56F8014 Block Diagram
Freescale Semiconductor
Preliminary
56F8014 Technical Data, Rev. 3
3



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56F8014 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . .
1.1. 56F8014 Features . . . . . . . . . . . . . . . . . . . . 5
1.2. 56F8014 Description . . . . . . . . . . . . . . . . . . . 6
1.3. Award-Winning Development Environment . . 7
1.4. Architecture Block Diagram . . . . . . . . . . . . . . 7
1.5. Product Documentation . . . . . . . . . . . . . . . . 11
1.6. Data Sheet Conventions. . . . . . . . . . . . . . . . 11
5
Part 2: Signal/Connection Descriptions . . . 12
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2. 56F8014 Signal Pins . . . . . . . . . . . . . . . . . . 15
Part 3: OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 24
3.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 26
3.5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . 27
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 27
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2. Interrupt Vector Table . . . . . . . . . . . . . . . . . 27
4.3. Program Map . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.5. EOnCE Memory Map . . . . . . . . . . . . . . . . . 31
4.6. Peripheral Memory Mapped Registers . . . . 32
Part 5: Interrupt Controller (ITCN) . . . . . . . . 42
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3. Functional Description . . . . . . . . . . . . . . . . 42
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 44
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . . 44
5.6. Register Descriptions . . . . . . . . . . . . . . . . . . 45
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Part 6: System Integration Module (SIM) . . 62
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3. Register Descriptions . . . . . . . . . . . . . . . . . . 63
6.4. Clock Generation Overview . . . . . . . . . . . . 76
6.5. Power-Down Modes . . . . . . . . . . . . . . . . . . 77
6.6. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.7. Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.8. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Part 7: Security Features. . . . . . . . . . . . . . . 82
7.1. Operation with Security Enabled . . . . . . . . . 82
7.2. Flash Access Lock and Unlock Mechanisms 82
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 84
8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . . 84
8.3. Reset Values . . . . . . . . . . . . . . . . . . . . . . . . 86
Part 9: Joint Test Action Group (JTAG) . . .91
9.1. 56F8014 Information . . . . . . . . . . . . . . . . . . 91
Part 10: Specifications . . . . . . . . . . . . . . . . .91
10.1. General Characteristics . . . . . . . . . . . . . . . 91
10.2. DC Electrical Characteristics . . . . . . . . . . . 95
10.3. AC Electrical Characteristics . . . . . . . . . . . 98
10.4. Flash Memory Characteristics . . . . . . . . . . 98
10.5. External Clock Operation Timing . . . . . . . . 99
10.6. Phase Locked Loop Timing . . . . . . . . . . . . 99
10.7. Relaxation Oscillator Timing. . . . . . . . . . . 100
10.8. Reset, Stop, Wait, Mode Select, and Interrupt
Timing . . . . . . . . . . . . . . . . . . . . . 101
10.9. Serial Peripheral Interface (SPI) Timing . 102
10.10. Quad Timer Timing . . . . . . . . . . . . . . . . 105
10.11. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . . . . 106
10.12. Inter-Integrated Circuit Interface
(I2C) Timing . . . . . . . . . . . . . . . . 107
10.13. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 108
10.14. Analog-to-Digital Converter
(ADC) Parameters 109
10.15. Equivalent Circuit for ADC Inputs . . . . . 110
10.16. Power Consumption . . . . . . . . . . . . . . . 111
Part 11: Packaging . . . . . . . . . . . . . . . . . . .113
11.1. 56F8014 Package and Pin-Out Information 113
Part 12: Design Considerations . . . . . . . . .116
12.1. Thermal Design Considerations . . . . . . . 116
12.2. Electrical Design Considerations . . . . . . . 117
Part 13: Ordering Information . . . . . . . . . .119
Part 14: Appendix . . . . . . . . . . . . . . . . . . . .120
56F8014 Technical Data, Rev. 3
4 Freescale Semiconductor
Preliminary



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