MC1496B Datasheet PDF - Motorola

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MC1496B
Motorola

Part Number MC1496B
Description BALANCED MODULATORS/DEMODULATORS
Page 12 Pages


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MC1496, B
Balanced Modulators/
Demodulators
These devices were designed for use where the output voltage is a
product of an input voltage (signal) and a switching function (carrier). Typical
applications include suppressed carrier and amplitude modulation,
synchronous detection, FM detection, phase detection, and chopper
applications. See Motorola Application Note AN531 for additional design
information.
Excellent Carrier Suppression –65 dB typ @ 0.5 MHz
Excellent Carrier Suppression –50 dB typ @ 10 MHz
Adjustable Gain and Signal Handling
Balanced Inputs and Outputs
High Common Mode Rejection –85 dB typical
This device contains 8 active transistors.
BALANCED
MODULATORS/DEMODULATORS
SEMICONDUCTOR
TECHNICAL DATA
14
1
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
P SUFFIX
PLASTIC PACKAGE
CASE 646
14
1
PIN CONNECTIONS
IC = 500 kHz, IS = 1.0 kHz
0
Figure 1. Suppressed
Cawrwrwi.eDartaSOheuett4Up.cuomt
Waveform
Signal Input 1
Gain Adjust 2
Gain Adjust 3
Signal Input 4
Bias 5
Output 6
N/C 7
14 VEE
13 N/C
12 Output
11 N/C
10 Carrier Input
9 N/C
8 Input Carrier
IC = 500 kHz
IS = 1.0 kHz
ORDERING INFORMATION
Operating
20
Figure 2. Suppressed
Device Temperature Range Package
Carrier Spectrum
MC1496D
MC1496P
TA = 0°C to +70°C
SO–14
Plastic DIP
40
60
499 kHz 500 kHz 501 kHz
MC1496BP TA = –40°C to +125°C Plastic DIP
Figure 4. Amplitude–Modulation Spectrum
10
IC = 500 kHz
8.0 IS = 1.0 kHz
Figure 3. Amplitude
Modulation Output
Waveform
6.0
4.0
2.0
IC = 500 kHz
IS = 1.0 kHz
0
499 kHz 500 kHz 501 kHz
MOTOROLA ANALOG IC DEVICE DATA
© Motorola, Inc. 1996
Rev 4
1



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MC1496, B
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Symbol
Applied Voltage
(V6 – V8, V10 – V1, V12 – V8, V12 – V10, V8 – V4,
V8 – V1, V10 – V4, V6 – V10, V2 – V5, V3 – V5)
V
Differential Input Signal
V8 – V10
V4 – V1
Maximum Bias Current
Thermal Resistance, Junction–to–Air
Plastic Dual In–Line Package
I5
RθJA
Operating Temperature Range
Storage Temperature Range
TA
Tstg
NOTE: ESD data available upon request.
Value
30
+5.0
±(5 + I5Re)
10
100
0 to +70
–65 to +150
Unit
Vdc
Vdc
mA
°C/W
°C
°C
ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, VEE = –8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 k, Re = 1.0 k, TA = Tlow to Thigh,
all input and output characteristics are single–ended, unless otherwise noted.)
Characteristic
Fig. Note Symbol Min Typ Max
Unit
Carrier Feedthrough
VC = 60 mVrms sine wave and
offset adjusted to zero
VC = 300 mVpp square wave:
offset adjusted to zero
offset not adjusted
fC = 1.0 kHz
fC = 10 MHz
fC = 1.0 kHz
fC = 1.0 kHz
51
VCFT
µVrms
– 40 –
– 140 –
mVrms
– 0.04 0.4
– 20 200
Carrier Suppression
fS = 10 kHz, 300 mVrms
fC = 500 kHz, 60 mVrms sine wave
fC = 10 MHz, 60 mVrms sine wave
52
VCS
40 65
– 50
dB
k
Transadmittance Bandwidth (Magnitude) (RL = 50 )
Carrier Input Port, VC = 60 mVrms sine wave
fS = 1.0 kHz, 300 mVrms sine wave
Signal Input Port, VS = 300 mVrms sine wave
|VC| = 0.5 Vdc
8 8 BW3dB
MHz
– 300 –
– 80 –
Signal Gain (VS = 100 mVrms, f = 1.0 kHz; | VC|= 0.5 Vdc)
10 3
AVS
2.5 3.5
V/V
Single–Ended Input Impedance, Signal Port, f = 5.0 MHz
Parallel Input Resistance
Parallel Input Capacitance
6–
rip
– 200 –
k
cip – 2.0 – pF
Single–Ended Output Impedance, f = 10 MHz
Parallel Output Resistance
Parallel Output Capacitance
Input Bias Current
IbS +
I1 )
2
I4 ;
IbC +
I8
) I10
2
6–
7–
rop – 40 – k
coo – 5.0 – pF
µA
IbS – 12 30
IbC – 12 30
Input Offset Current
IioS = I1–I4; IioC = I8–I10
7–
IioS
IioC
– 0.7 7.0
– 0.7 7.0
µA
Average Temperature Coefficient of Input Offset Current
(TA = –55°C to +125°C)
7
TCIio
– 2.0 –
nA/°C
Output Offset Current (I6–I9)
7–
Ioo
– 14 80
µA
Average Temperature Coefficient of Output Offset Current
(TA = –55°C to +125°C)
7 – TCIoo– 90 – nA/°C
Common–Mode Input Swing, Signal Port, fS = 1.0 kHz
94
CMV
– 5.0 –
Vpp
Common–Mode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc
9–
ACM
– –85 –
dB
Common–Mode Quiescent Output Voltage (Pin 6 or Pin 9)
10 –
Vout – 8.0 – Vpp
Differential Output Voltage Swing Capability
10 –
Vout – 8.0 – Vpp
Power Supply Current I6 +I12
Power Supply Current I14
76
ICC – 2.0 4.0 mAdc
IEE – 3.0 5.0
DC Power Dissipation
75
PD
– 33 –
mW
2 MOTOROLA ANALOG IC DEVICE DATA



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MC1496, B
GENERAL OPERATING INFORMATION
Carrier Feedthrough
Carrier feedthrough is defined as the output voltage at
carrier frequency with only the carrier applied (signal
voltage = 0).
Carrier null is achieved by balancing the currents in the
differential amplifier by means of a bias trim potentiometer
(R1 of Figure 5).
Carrier Suppression
Carrier suppression is defined as the ratio of each
sideband output to carrier output for the carrier and signal
voltage levels specified.
Carrier suppression is very dependent on carrier input
level, as shown in Figure 22. A low value of the carrier does
not fully switch the upper switching devices, and results in
lower signal gain, hence lower carrier suppression. A higher
than optimum carrier level results in unnecessary device and
circuit carrier feedthrough, which again degenerates the
suppression figure. The MC1496 has been characterized
with a 60 mVrms sinewave carrier input signal. This level
provides optimum carrier suppression at carrier frequencies
in the vicinity of 500 kHz, and is generally recommended for
balanced modulator applications.
Carrier feedthrough is independent of signal level, VS.
Thus carrier suppression can be maximized by operating
with large signal levels. However, a linear operating mode
must be maintained in the signal–input transistor pair – or
harmonics of the modulating signal will be generated and
appear in the device output as spurious sidebands of the
suppressed carrier. This requirement places an upper limit on
input–signal amplitude (see Figure 20). Note also that an
optimum carrier level is recommended in Figure 22 for good
carrier suppression and minimum spurious sideband
generation.
At higher frequencies circuit layout is very important in
order to minimize carrier feedthrough. Shielding may be
necessary in order to prevent capacitive coupling between
the carrier input leads and the output leads.
Signal Gain and Maximum Input Level
Signal gain (single–ended) at low frequencies is defined
as the voltage gain,
AVS +
Vo
VS
+
ReR)L2re
where
re +
26 mV
I5(mA)
A constant dc potential is applied to the carrier input terminals
to fully switch two of the upper transistors “on” and two
transistors “off” (VC = 0.5 Vdc). This in effect forms a cascode
differential amplifier.
Linear operation requires that the signal input be below a
critical value determined by RE and the bias current I5.
pVS I5 RE (Volts peak)
Note that in the test circuit of Figure 10, VS corresponds to a
maximum value of 1.0 V peak.
Common Mode Swing
The common–mode swing is the voltage which may be
applied to both bases of the signal differential amplifier,
without saturating the current sources or without saturating
the differential amplifier itself by swinging it into the upper
switching devices. This swing is variable depending on the
particular circuit and biasing conditions chosen.
Power Dissipation
Power dissipation, PD, within the integrated circuit package
should be calculated as the summation of the voltage–current
products at each port, i.e. assuming V12 = V6, I5 = I6 = I12
and ignoring base current, PD = 2 I5 (V6 – V14) + I5)
V5 – V14 where subscripts refer to pin numbers.
Design Equations
The following is a partial list of design equations needed to
operate the circuit with other supply voltages and input
conditions.
A. Operating Current
The internal bias currents are set by the conditions at Pin 5.
Assume:
then :
I5 = I6 = I12,
ttIB IC for all transistors
+ * * *R5
Vf
I5
where: R5 is the resistor between
500 W where: Pin 5 and ground
where: φ = 0.75 at TA = +25°C
The MC1496 has been characterized for the condition
I5 = 1.0 mA and is the generally recommended value.
B. Common–Mode Quiescent Output Voltage
V6 = V12 = V+ – I5 RL
Biasing
The MC1496 requires three dc bias voltage levels which
must be set externally. Guidelines for setting up these three
levels include maintaining at least 2.0 V collector–base bias
on all transistors while not exceeding the voltages given in
the absolute maximum rating table;
w w30 Vdc [(V6, V12) – (V8, V10)] 2 Vdc
w w30 Vdc [(V8, V10) – (V1, V4)] 2.7 Vdc
w w30 Vdc [(V1, V4) – (V5)] 2.7 Vdc
The foregoing conditions are based on the following
approximations:
V6 = V12, V8 = V10, V1 = V4
Bias currents flowing into Pins 1, 4, 8 and 10 are transistor
base currents and can normally be neglected if external bias
dividers are designed to carry 1.0 mA or more.
Transadmittance Bandwidth
Carrier transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:
+ +g21C
io (each sideband)
vs (signal)
Vo
0
Signal transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:
+ + +g21S
io (signal)
vs (signal)
Vc
0.5 Vdc, Vo
0
MOTOROLA ANALOG IC DEVICE DATA
3



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MC1496, B
Coupling and Bypass Capacitors
Capacitors C1 and C2 (Figure 5) should be selected for a
reactance of less than 5.0 at the carrier frequency.
Output Signal
The output signal is taken from Pins 6 and 12 either
balanced or single–ended. Figure 11 shows the output levels
of each of the two output sidebands resulting from variations
in both the carrier and modulating signal inputs with a
single–ended output connection.
Negative Supply
VEE should be dc only. The insertion of an RF choke in
series with VEE can enhance the stability of the internal
current sources.
Signal Port Stability
Under certain values of driving source impedance,
oscillation may occur. In this event, an RC suppression
network should be connected directly to each input using
short leads. This will reduce the Q of the source–tuned
circuits that cause the oscillation.
Signal Input
(Pins 1 and 4)
510
10 pF
An alternate method for low–frequency applications is to
insert a 1.0 kresistor in series with the input (Pins 1, 4). In
this case input current drift may cause serious degradation of
carrier suppression.
TEST CIRCUITS
Figure 5. Carrier Rejection and Suppression
VCC
12 Vdc
1.0 k 1.0 k
Carrier
Input
C2
0.1 µF
VC
VS
Modulating
Signal Input 10 k
51 C1
0.1 µF
10 k 51
Re RL
RL
82
1.0 k
3.9 k
3
3.9 k
10
1 MC1496
6
I9 I6
+ Vo
4 12 – Vo
51 14 5
50 k
R1
Carrier Null
I10 I5
V–
–8.0 Vdc
VEE
6.8 k
Figure 6. Input–Output Impedance
Re = 1.0 k
2
0.5 V 8
+ – 10
3
1 MC1496 6
Zin 4
12
14 5
6.8 k
Z+ouVto
– Vo
–8.0 Vdc
NOTE: Shielding of input and output leads may be needed
to properly perform these tests.
Figure 7. Bias and Offset Currents
VCC
12 Vdc
1.0 k
I7
I8
1.0 k I1
I4
Re = 1.0 k
2
8
10
3 2.0 k
I6
1 MC1496 6 I9
4 12
14 5
I10 6.8 k
–8.0 Vdc
VEE
Figure 8. Transconductance Bandwidth
1.0 k
Carrier
Input 0.1 µF
VC
VS
Modulating
Signal Input
10 k
51 0.1 µF
10 k 51
50 k
Carrier Null
1.0 k
Re
1.0 k
23
8
10
1 MC1496 6
4 12
51 14 5
V–
–8.0 Vdc
VEE
6.8 k
VCC
12 Vdc
2.0 k
0.01
50 50 µF
+ Vo
– Vo
4 MOTOROLA ANALOG IC DEVICE DATA



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