MC100LVELT20 Datasheet PDF - ON Semiconductor

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MC100LVELT20
ON Semiconductor

Part Number MC100LVELT20
Description LVTTL/LVCMOS to Differential LVPECL Translator
Page 6 Pages


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MC100LVELT20
3.3 V LVTTL/LVCMOS to
Differential LVPECL
Translator
Description
The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL
translator. Because PECL (Positive ECL) levels are used, only + 3.3 V
and ground are required. The small outline SOIC8 package and the
single gate of the MC100LVELT20 makes it ideal for those
applications where space, performance, and low power are at a
premium.
The 100 Series contains temperature compensation.
Features
390 ps Typical Propagation Delay
Maximum Input Clock Frequency > 0.8 GHz Typical
Operating Range VCC = 3.0 V to 3.6 V with GND = 0 V
PNP TTL Input for Minimal Loading
Q Output will Default HIGH with Input Open
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
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8
1
SOIC8 NB
D SUFFIX
CASE 75107
MARKING DIAGRAM
8
KVT20
ALYW
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
Package Shipping
MC100LVELT20DG
SOIC8 NB
(Pb-Free)
MC100LVELT20DR2G SOIC-8 NB
(Pb-Free)
98 Units/Tube
2500/Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 Rev. 1
1
Publication Order Number:
MC100LVELT20/D



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NC 1
Q2
Q3
LVPECL
NC 4
MC100LVELT20
8 VCC
LVTTL
7D
6 NC
Table 1. PIN DESCRIPTION
Pin Function
Q, Q
Differential PECL Outputs
D LVTTL Input
VCC
GND
Positive Supply
Ground
NC No Connect
5 GND
(Top View)
Figure 1. 8-Lead Pinout and Logic Diagram
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC8 NB
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
N/A
N/A
> 1.5 kV
> 200 V
> 2 kV
Pb-Free Pkg
Level 1
UL 94 V0 @ 0.125 in
150 Devices
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC Power Supply
VI Input Voltage
Iout Output Current
GND = 0 V
GND = 0 V
Continuous
Surge
VI VCC
6V
6V
50 mA
100
TA Operating Temperature Range
Tstg Storage Temperature Range
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC8 NB
40 to +85
65 to +150
190
130
°C
°C
°C/W
qJC Thermal Resistance (Junction-to-Case)
Tsol Wave Solder (Pb-Free)
Standard Board
SOIC8 NB
41 to 44
265
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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MC100LVELT20
Table 4. LVTTL INPUT DC CHARACTERISTICS (VCC = 3.3 V, GND = 0 V, TA = 40°C to +85°C)
Symbol
Characteristic
Min Typ
Max Unit
IIH Input HIGH Current (Vin = 2.7 V)
IIHH Input HIGH Current MAX (Vin = 6.0 V)
IIL Input LOW Current (Vin = 0.5 V)
VIK Input Clamp Voltage (Iin = 18 mA)
VIH Input HIGH Voltage
VIL Input LOW Voltage
20 mA
100 mA
0.6 mA
1.2 V
2.0 V
0.8 V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. 100LVELT PECL OUTPUT DC CHARACTERISTICS (VCC = 3.3 V, GND = 0 V (Note 1))
40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
ICC Negative Power Supply Current
VOH Output HIGH Voltage (Note 2)
VOL Output LOW Voltage (Note 2)
20
2155
1355
25
2280
1480
30
2405
1605
22
2155
1355
27
2280
1480
32
2405
1605
23
2155
1355
28
2280
1480
33
2405
1605
mA
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Output parameters vary 1:1 with VCC.
2. All loading with 50ĂW to VCC 2.0 V.
Table 6. AC CHARACTERISTICS (VCC = 3.0 V to 3.6 V, GND = 0 V (Note 1))
40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
fmax
Maximum Input Clock Frequency
(Figure 2)
600 800
600 800
600 800
MHz
tPLH,
tPHL
tSKEW
tJITTER
Propagation Delay to
Output Differential
Device-to-Device Skew (Note 2)
Random Clock Jitter (RMS)
(Figure 2)
280 350 430 300 370 450 320 400 490 ps
250
<1 <2
250
<1 <2
250 ps
< 1 < 2 ps
tr Output Rise/Fall Times
70 100 225 80 120 225 90 140 225 ps
tf Q, Q
(20% 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Measured using a LVTTL source, 50% duty cycle clock source. All loading with 50ĂW to VCC 2.0 V.
2. Skew is measured between outputs under identical transitions.
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900
800
700
600
500
400
300
200
100
0
0
MC100LVELT20
Amplitude
Jitter
200 400 600 800
INPUT CLOCK FREQUENCY (MHz)
Figure 2. Output Voltage Amplitude (VOUTpp)/RMS Jitter
vs. Input Clock Frequency at Ambient Temperature
9
8
7
6
5
4
3
2
1
1000
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
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4



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