MBM29DS163TE Datasheet PDF - Fujitsu Media Devices


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MBM29DS163TE
Fujitsu Media Devices

Part Number MBM29DS163TE
Description (MBM29DS163BE/TE) FLASH MEMORY CMOS 16 M (2 M X 8/1 M X 16) BIT
Page 30 Pages

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FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20891-4E
FLASH MEMORY
CMOS
16 M (2 M × 8/1 M × 16) BIT Dual Operation
MBM29DS163TE/BE10
s DESCRIPTION
The MBM29DS163TE/BE is 16 M-bit, 1.8 V-only Flash memory organized as 2 M bytes of 8 bits each or 1 M
words of 16 bits each. The device is offered in 48-pin TSOP (1) and 48-ball FBGA packages. This device is
designed to be programmed in system with standard system 1.8 V VCC supply. 12.0 V VPP and 5.0 V VCC are not
required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers.
(Continued)
s PRODUCT LINE UP
Part No.
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
MBM29DS163TE/BE10
VCC
=
2.0
V +0.2
0.2
V
V
100
100
35
s PACKAGES
48-pin plastic TSOP (1)
Marking Side
48-pin plastic TSOP (1)
48-ball plastic FBGA
(FPT-48P-M19)
Marking Side
(FPT-48P-M20)
(BGA-48P-M11)



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MBM29DS163TE/BE10
(Continued)
The device is organized into two banks, Bank 1 and Bank 2, which can be considered to be two separate memory
arrays as far as certain operations are concerned. This device is the same as Fujitsu’s standard 1.8 V only Flash
memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of
the array while an embedded write (either a program or an erase) operation is simultaneously taking place on
the other bank.
The standard device offers access time 100 ns, allowing operation of high-speed microprocessors without wait
state. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) , and output
enable (OE) controls.
The device is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the
command register using standard microprocessor write timings. Register contents serve as input to an internal
state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase operations. Reading data out of the device is similar to reading
from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This invokes the Embedded Erase Algorithm which
is an internal algorithm that automatically preprograms the array if it is not already programmed before executing
the erase operation. During erase, the device automatically times the erase pulse widths and verify proper cell
margin.
A sector is typically erased and verified in 1.0 second (if already completely preprogrammed) .
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 1.8 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle is completed,
the device internally resets to the read mode.
The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program
Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read
mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the
Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode
and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word
at a time using the EPROM programming mechanism of hot electron injection.
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MBM29DS163TE/BE10
s FEATURES
0.23 µm Process Technology
Simultaneous Read/Write Operations (Dual Bank)
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations
Read-while-erase
Read-while-program
Single 1.8 V Read, Program, and Erase
Minimized system level power requirements
Compatible with JEDEC-standard Commands
Use the same software commands as E2PROMs
Compatible with JEDEC-standard Worldwide Pinouts
48-pin TSOP (1) (Package suffix : TN Normal Bend Type, TR Reversed Bend Type)
48-ball FBGA (Package suffix : PBT)
Minimum 100,000 Program/Erase Cycles
High Performance
100 ns maximum access time
Sector Erase Architecture
Eight 4 K word and thirty-one 32 K word sectors in word mode
Eight 8 K byte and thirty-one 64 K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
T = Top sector
B = Bottom sector
HiddenROM Region
64 K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
WP/ACC Input Pin
At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
At VIH, allows removal of boot sector protection
At VACC, increases program performance
Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
Program Suspend/Resume
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
Sector Group Protection
Hardware method disables any combination of sector groups from program or erase operations
Sector Group Protection Set function by Extended sector group protection command
Fast Programming Function by Extended Command
Temporary Sector Group Unprotection
Temporary sector group unprotection via the RESET pin.
In accordance with CFI (Common Flash Memory Interface)
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
3



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MBM29DS163TE/BE10
s PIN ASSIGNMENTS
A15
A14
A13
A12
A11
A10
A9
A8
A19
N.C.
WE
RESET
N.C.
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A1
A2
A3
A4
A5
A6
A7
A17
A18
RY/BY
WP/ACC
N.C.
RESET
WE
N.C.
A19
A8
A9
A10
A11
A12
A13
A14
A15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TSOP (1)
(Marking Side)
MBM29DS163TE/BE
Normal Bend
(FPT-48P-M19)
(Marking Side)
MBM29DS163TE/BE
Reverse Bend
(FPT-48P-M20)
48 A16
47 BYTE
46 VSS
45 DQ15/A-1
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE
27 VSS
26 CE
25 A0
25 A0
26 CE
27 VSS
28 OE
29 DQ0
30 DQ8
31 DQ1
32 DQ9
33 DQ2
34 DQ10
35 DQ3
36 DQ11
37 VCC
38 DQ4
39 DQ12
40 DQ5
41 DQ13
42 DQ6
43 DQ14
44 DQ7
45 DQ15/A-1
46 VSS
47 BYTE
48 A16
4
(Continued)




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