MBM29DL34BF Datasheet PDF - Fujitsu Media Devices


Fujitsu Media Devices

Part Number MBM29DL34BF
Description (MBM29DL34BF/TF) FLASH MEMORY CMOS 32 M (4 M X 8/2 M X 16) BIT
Page 30 Pages

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32 M (4 M × 8/2 M × 16) BIT Dual Operation
The MBM29DL34TF/BF are a 32 M-bit, 3.0 V-only Flash memory organized as 4 M bytes of 8 bits each or 2 M
words of 16 bits each. These devices are designed to be programmed in-system with the standard system 3.0 V
VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be
reprogrammed in standard EPROM programmers.
Part No.
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
2.7 V to 3.6 V
48-pin plastic TSOP (1)
48-ball plastic FBGA
Marking side

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MBM29DL34TF/BF are organized into two physical banks; Bank 1 and Bank 2, which can be considered to be
two separate memory arrays as far as certain operations are concerned. This device is the same as Fujitsu’s
standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access
from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simul-
taneously taking place on the other bank.
In the device, a design concept called Sliding Bank Architecture is implemented. Using this concept the device
can execute simultaneous operation between Bank 1 and Bank 2(Refer to “1. Simultaneous Operation” in
The standard device offers access times 70 ns allowing operation of high-speed microprocessors without the
wait. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) and output enable
(OE) controls.
The MBM29DL34TF/BF support pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the device is
similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This will invoke the Embedded Erase AlgorithmTM
which is an internal algorithm that automatically preprograms the array if it is not already programmed before
executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies
the proper cell margin.
Each sector is typically erased and verified in 0.5 second (if already completely preprogrammed) .
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the device internally return to the read mode.
The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program
Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read
mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the
Embedded ProgramTM * Algorithm or Embedded EraseTM * Algorithm, the device is automatically reset to the
read mode and have erroneous data stored in the address locations being programmed or erased. These
locations need rewriting after the Reset. Resetting the device enables the system’s microprocessor to read the
boot-up firmware from the Flash memory.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all
bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/
word at a time using the EPROM programming mechanism of hot electron injection.
*: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

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0.17 µm Process Technology
Simultaneous Read/Write Operations (Dual Bank)
Bank 1 : 8 Mbit
Bank 2 : 24 Mbit
Host system can program or erase in one bank, then immediately and simultaneously read and
from the other bank.
Zero latency between read and write operation.
Read - while - erase
Read - while - program
Single 3.0 V Read, Program, and Erase
Minimizes system level power requirements
Compatible with JEDEC-standard Commands
Uses same software commands as E2PROMs
Compatible with JEDEC-standard World-wide Pinouts
48-pin TSOP (1) (Package suffix : TN Normal Bend Type, TR Reversed Bend Type)
48-ball FBGA (Package suffix : PBT)
• Minimum 100,000 Program/Erase Cycles
High Performance
70 ns maximum access time
Sector Erase Architecture
Eight 4 K word and sixty-three 32 K word sectors in word mode
Eight 8 K byte and sixty-three 64 K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
T = Top sector
B = Bottom sector
HiddenROM Region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
WP/ACC Input Pin
At VIL, allows protection of “outermost” 2 × 8 bytes on boot sectors, regardless of sector protection/unprotection
At VIH, allows removal of boot sector protection
At VACC, increases program performance
Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready/Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
Low VCC write inhibit 2.5 V
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device

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Sector Group Protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
Temporary Sector Group Unprotection
Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
Device Part Number
Bank and Sector Organization Table
Bank 1
Bank A (SA70 to 48)
Bank A (SA0 to 22)
Bank 2
Bank B (SA47 to 0)
Bank B (SA23 to 70)

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