The device provides truly high performance non-volatile memory solution. The device offers fast burst access
frequency of 66 MHz with initial access times of 56 ns at Handshaking mode, allowing operation of high-speed
microprocessors without wait states. To eliminate bus connection the device has separate chip enable (CE),
write enable (WE), address valid (AVD) and output enable (OE) controls. For burst operations, the device
additionally requires Ready (RDY) at Handshaking mode, and Clock (CLK). This implementation allows easy
interface with minimal glue logic to a wide range of microprocessors/ microcontrollers for high performance read
The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset
the burst length and wrap through the same memory space. At 66 MHz, the device provides a burst access of
11 ns with a latency of 56 ns at 30 pF (Handshaking mode).
The dual operation function provides simultaneous operation by dividing the memory space into four banks. The
device can improve overall system performance by allowing a host system to program or erase in one bank,
then immediately and simultaneously read from another bank, with zero latency. This releases the system from
waiting for the completion of program or erase operations.
The device is command set compatible with JEDEC standard E2PROMs. Commands are written to the command
register using standard microprocessor write timing. Register contents serve as inputs to an internal state-
machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and
data needed for the programming and erase operations. Reading data out of the device is similar to reading
from 5.0 V and 12.0 V Flash or EPROM devices.
The device is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margins. Typically, each 32K words sector can be programmed and verified in about 0.3 second.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
Any individual sector is typically erased and verified in 0.5 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The Enhanced VI/O (VCCQ) feature allows the output voltage generated on the device to be determined based on
the VI/O level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving signals
to and from other 1.8 V devices on the same bus.
The device features single 1.8 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. The end of program or erase is
detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, output pin. Once the end of a program or
erase cycle has been completed, the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simulta-
neously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.