MAX1438B Datasheet PDF - Maxim Integrated Products

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MAX1438B
Maxim Integrated Products

Part Number MAX1438B
Description 1.8V ADC
Page 21 Pages


MAX1438B datasheet pdf
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19-4630; Rev 0; 7/09
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EVAALVUAAILTAIOBNLEKIT
Octal, 12-Bit, 64Msps, 1.8V ADC
with Serial LVDS Outputs
General Description
The MAX1438B octal, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction incorporating a
fully differential signal path. This ADC is optimized for
low-power and high-dynamic performance in medical
imaging instrumentation and digital communications
applications. The MAX1438B operates from a 1.8V sin-
gle supply and consumes only 913mW (114mW per
channel) while delivering a 69.9dB (typ) signal-to-noise
ratio (SNR) at a 5.3MHz input frequency. In addition to
low operating power, the MAX1438B features a low-
power standby mode for idle periods.
An internal 1.24V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference struc-
ture allows the use of an external reference for applica-
tions requiring increased accuracy or a different input
voltage range. The reference architecture is optimized
for low noise.
A single-ended clock controls the data-conversion
process. An internal duty-cycle equalizer compensates
for wide variations in clock duty cycle. An on-chip
phase-locked loop (PLL) generates the high-speed ser-
ial low-voltage differential signal (LVDS) clock.
The MAX1438B has self-aligned serial LVDS outputs for
data, clock, and frame-alignment signals. The output
data is presented in two’s-complement format.
The MAX1438B offers a maximum sample rate of
64Msps. This device is available in a small, 10mm x
10mm x 0.8mm, 68-pin thin QFN package with exposed
pad and is specified for the extended industrial (-40°C
to +85°C) temperature range.
Applications
Ultrasound and Medical Imaging
Instrumentation
Multichannel Communications
Features
Excellent Dynamic Performance
69.9dB SNR at 5.3MHz
94dBc SFDR at 5.3MHz
Ultra-Low Power
114mW per Channel (Normal Operation)
Serial LVDS Outputs
Pin-Selectable LVDS/SLVS (Scalable Low-Voltage
Signal) Mode
LVDS Outputs Support Up to 30in FR4 Backplane
Connections
Test Mode for Digital Signal Integrity
Fully Differential Analog Inputs
Wide Differential Input Voltage Range (1.4VP-P)
On-Chip 1.24V Precision Bandgap Reference
Clock Duty-Cycle Equalizer
Compact, 68-Pin Thin QFN Package with Exposed
Pad
Evaluation Kit Available (Order MAX1437BEVKIT)
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1438BETK+ -40°C to +85°C
68 Thin QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.



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Octal, 12-Bit, 64Msps, 1.8V ADC
with Serial LVDS Outputs
ABSOLUTE MAXIMUM RATINGS
AVDD to GND........................................................-0.3V to +2.0V
CVDD to GND........................................................-0.3V to +3.6V
OVDD to GND .......................................................-0.3V to +2.0V
IN_P, IN_N to GND .................................-0.3V to (VAVDD + 0.3V)
CLK to GND ...........................................-0.3V to (VCVDD + 0.3V)
OUT_P, OUT_N, FRAME_,
CLKOUT_ to GND ..............................-0.3V to (VOVDD + 0.3V)
DT, SLVS/LVDS, LVDSTEST, PLL_, STBY
REFIO, REFADJ, CMOUT to GND......-0.3V to (VAVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
68-Pin Thin QFN, 10mm x 10mm x 0.8mm
(derate 70mW/°C above +70°C) ................................4000mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V, external VREFIO = 1.24V, CREFIO to GND = 0.1µF || 1.0µF, CREFP to GND =
10µF, CREFN to GND = 10µF, fCLK = 64MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DC ACCURACY (Note 2)
Resolution
N
12 Bits
Integral Nonlinearity
INL
±0.4
±2.5
LSB
Differential Nonlinearity
DNL No missing codes over temperature
±0.25
±1
LSB
Offset Error
±0.5
%FS
Gain Error
-3 ±0.5 +2 %FS
ANALOG INPUTS (IN_P, IN_N)
Input Differential Range
Common-Mode Voltage Range
VID
VCMO
Differential input
1.4
0.76
VP-P
V
Common-Mode Voltage Range
Tolerance
(Note 3)
±50 mV
Differential Input Impedance
Differential Input Capacitance
CONVERSION RATE
RIN Switched capacitor load
CIN
2 k
12.5 pF
Maximum Conversion Rate
Minimum Conversion Rate
Data Latency
fSMAX
fSMIN
64
4.0
6.5
MHz
MHz
Cycles
DYNAMIC CHARACTERISTICS (Differential Inputs, 4096-Point FFT) (Note 2)
Signal-to-Noise Ratio
Signal-to-Noise and Distortion
Effective Number of Bits
Spurious-Free Dynamic Range
SNR
SINAD
ENOB
SFDR
fIN = 5.3MHz at -0.5dBFS
fIN = 20MHz at -0.5dBFS
fIN = 5.3MHz at -0.5dBFS
fIN = 20MHz at -0.5dBFS
fIN = 5.3MHz at -0.5dBFS
fIN = 20MHz at -0.5dBFS
fIN = 5.3MHz at -0.5dBFS
fIN = 20MHz at -0.5dBFS
67
67
10.8
79
69.9
69.6
69.8
69.6
11.4
11.4
94
93
dB
dB
Bits
dBc
2 _______________________________________________________________________________________



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Octal, 12-Bit, 64Msps, 1.8V ADC
with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V , external VREFIO = 1.24V, CREFIO to GND = 0.1µF || 1.0µF, CREFP to GND =
10µF, CREFN to GND = 10µF, fCLK = 64MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Total Harmonic Distortion
Intermodulation Distortion
THD
IMD
fIN = 5.3MHz at -0.5dBFS
fIN = 20MHz at -0.5dBFS
f1 = 5.3MHz at -6.5dBFS
f2 = 6.3MHz at -6.5dBFS
-95
dBc
-92 -79
89.3 dBc
Third-Order Intermodulation
IM3
f1 = 5.3MHz at -6.5dBFS
f2 = 6.3MHz at -6.5dBFS
97.5 dBc
Aperture Jitter
Aperture Delay
Small-Signal Bandwidth
tAJ
tAD
SSBW
Figure 10
Figure 10
Input at -20dBFS
< 0.4
1
100
psRMS
ns
MHz
Full-Power Bandwidth
LSBW Input at -0.5dBFS
100 MHz
Output Noise
IN_P = IN_N
0.44
LSBRMS
Overrange Recovery Time
tOR RS = 25, CS = 50pF
1
Clock
cycle
INTERNAL REFERENCE
REFADJ Internal Reference-Mode
Enable Voltage
(Note 4)
0.1 V
REFADJ Low-Leakage Current
1.5 mA
REFIO Output Voltage
Reference Temperature
Coefficient
VREFIO
TCREFIO
1.18 1.24 1.30
V
120 ppm/°C
EXTERNAL REFERENCE
REFADJ External Reference-
Mode Enable Voltage
(Note 4)
VAVDD -
0.1V
V
REFADJ High-Leakage Current
200 µA
REFIO Input Voltage
1.24 V
REFIO Input Voltage Tolerance
±5 %
REFIO Input Current
IREFIO
COMMON-MODE OUTPUT (CMOUT)
< 1 µA
CMOUT Output Voltage
CLOCK INPUT (CLK)
VCMOUT
0.76 V
Input High Voltage
VCLKH
0.8 x
VAVDD
V
Input Low Voltage
Clock Duty Cycle
VCLKL
0.2 x
VAVDD
V
50 %
Clock Duty-Cycle Tolerance
±30 %
Input Leakage
Input Capacitance
DIIN
DCIN
Input at GND
Input at VAVDD
5
µA
80
5 pF
_______________________________________________________________________________________ 3



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Octal, 12-Bit, 64Msps, 1.8V ADC
with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 1.8V, VGND = 0V, external VREFIO = 1.24V, CREFIO to GND = 0.1µF || 1.0µF, CREFP to GND =
10µF, CREFN to GND = 10µF, fCLK = 64MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS, STBY)
Input High Threshold
VIH
CONDITIONS
MIN TYP
0.8 x
VAVDD
Input Low Threshold
VIL
Input Leakage
DIIN
Input at GND
Input at VAVDD
Input Capacitance
DCIN
LVDS OUTPUTS (OUT_P, OUT_N), SLVS/LVDS = 0
5
Differential Output Voltage
VOHDIFF RTERM = 100
250
Output Common-Mode Voltage
VOCM RTERM = 100
1.125
Rise Time (20% to 80%)
tRL RTERM = 100, CLOAD = 5pF
350
Fall Time (80% to 20%)
tFL RTERM = 100, CLOAD = 5pF
350
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1
Differential Output Voltage
VOHDIFF RTERM = 100
205
Output Common-Mode Voltage
Rise Time (20% to 80%)
Fall Time (80% to 20%)
STANDBY MODE (STBY)
VOCM
tRS
tFS
RTERM = 100
RTERM = 100, CLOAD = 5pF
RTERM = 100, CLOAD = 5pF
220
320
320
STBY Fall to Output Enable
STBY Rise to Output Disable
POWER REQUIREMENTS
tENABLE
tDISABLE
200
60
AVDD Supply Voltage Range
OVDD Supply Voltage Range
CVDD Supply Voltage Range
AVDD Supply Current
VAVDD
1.7 1.8
VOVDD
1.7 1.8
VCVDD
1.7 1.8
IAVDD
fIN = 20MHz
at -0.5dBFS
STBY = 0, DT = 0
STBY = 0, DT = 1
STBY = 1, no clock input
422
422
37
OVDD Supply Current
IOVDD
fIN = 20MHz
at -0.5dBFS
STBY = 0
STBY = 0, DT = 1
STBY = 1, no clock input
85
85
16
CVDD Supply Current
CVDD is used only to bias ESD-protection
ICVDD diodes on CLK input, Figure 2
0
Power Dissipation
PDISS fIN = 20MHz at -0.5dBFS
913
MAX UNITS
0.2 x
VAVDD
5
80
V
V
µA
pF
450
1.375
mV
V
ps
ps
mV
mV
ps
ps
µs
ns
1.9 V
1.9 V
3.5 V
465
mA
110
1035
mA
µA
mA
mW
4 _______________________________________________________________________________________



MAX1438B datasheet pdf
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