MAX1275 Datasheet PDF - Maxim Integrated Products

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MAX1275
Maxim Integrated Products

Part Number MAX1275
Description (MAX1274 / MAX1275) 12-Bit ADCs
Page 18 Pages


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19-3158; Rev 0; 1/04
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1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
General Description
The MAX1274/MAX1275 low-power, high-speed, serial-
output, 12-bit, analog-to-digital converters (ADCs) oper-
ate at up to 1.8Msps. These devices feature true-differen-
tial inputs, offering better noise immunity, distortion
improvements, and a wider dynamic range over single-
ended inputs. A standard SPI™/QSPI™/MICROWIRE™
interface provides the clock necessary for conversion.
These devices easily interface with standard digital signal
processor (DSP) synchronous serial interfaces.
The MAX1274/MAX1275 operate from a single +4.75V to
+5.25V supply voltage and require an external reference.
The MAX1274 has a unipolar analog input, while the
MAX1275 has a bipolar analog input. These devices fea-
ture a partial power-down mode and a full power-down
mode for use between conversions, which lower the sup-
ply current to 1mA (typ) and 1µA (max), respectively. Also
featured is a separate power-supply input (VL), which
allows direct interfacing to +1.8V to VDD digital logic. The
fast conversion speed, low-power dissipation, excellent
AC performance, and DC accuracy (±1 LSB INL) make
the MAX1274/MAX1275 ideal for industrial process con-
trol, motor control, and base-station applications.
The MAX1274/MAX1275 come in a 12-pin TQFN pack-
age, and are available in the commercial (0°C to +70°C)
and extended (-40°C to +85°C) temperature ranges.
Data Acquisition
Bill Validation
Motor Control
Applications
Communications
Portable Instruments
Pin Configuration
Features
1.8Msps Sampling Rate
Only 45mW (typ) Power Dissipation
Only 1µA (max) Shutdown Current
High-Speed, SPI-Compatible, 3-Wire Serial Interface
70dB S/(N + D) at 525kHz Input Frequency
Internal True-Differential Track/Hold (T/H)
External Reference
No Pipeline Delays
Small 12-Pin TQFN Package
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
MAX1274ACTC-T
MAX1274BCTC-T
MAX1274AETC-T
MAX1274BETC-T
MAX1275ACTC-T
MAX1275BCTC-T
MAX1275AETC-T
MAX1275BETC-T
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
12 TQFN-12
12 TQFN-12
12 TQFN-12
12 TQFN-12
12 TQFN-12
12 TQFN-12
12 TQFN-12
12 TQFN-12
INPUT
Unipolar
Unipolar
Unipolar
Unipolar
Bipolar
Bipolar
Bipolar
Bipolar
Typical Operating Circuit
TOP VIEW
AIN+ N.C. SCLK
12 11 10
AIN- 1
REF 2
RGND 3
MAX1274
MAX1275
9 CNVST
8 DOUT
7 VL
456
VDD N.C. GND
TQFN
4.75V TO +5.25V
+1.8V TO VDD
10µF
DIFFERENTIAL +
INPUT
VOLTAGE -
REF
4.7µF
0.01µF
0.01µF
VDD
0.01µF
VL
AIN+ DOUT
AIN-
MAX1274
MAX1275 CNVST
SCLK
REF
RGND
GND
10µF
µC/DSP
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.



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1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
VL to GND ...................-0.3V to the lower of (VDD + 0.3V) or +6V
Digital Inputs
to GND ....................-0.3V to the lower of (VDD + 0.3V) or +6V
Digital Output
to GND .......................-0.3V to the lower of (VL + 0.3V) or +6V
Analog Inputs and
REF to GND.............-0.3V to the lower of (VDD + 0.3V) or +6V
RGND to GND .......................................................-0.3V to +0.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
12-Pin TQFN (derate 16.9mW/°C above +70°C) ......1349mW
Operating Temperature Ranges
MAX127_ CTC ...................................................0°C to +70°C
MAX127_ ETC.................................................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V ±5%, VL = VDD, VREF = 4.096V, fSCLK = 28.8MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DC ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
INL
DNL
(Note 1)
(Note 2)
MAX127_A
MAX127_B
MAX127_A
MAX127_B
12
-1.0
-1.75
-1.0
-1.0
+1.0
+1.75
+1.0
+1.75
±6.0
Bits
LSB
LSB
LSB
Offset-Error Temperature
Coefficient
±1 ppm/°C
Gain Error
Offset nulled
Gain Temperature Coefficient
DYNAMIC SPECIFICATIONS (fIN = 525kHz sine wave, VIN = VREF, unless otherwise noted.)
Signal-to-Noise Plus Distortion
SINAD
MAX127_A
MAX127_B
69
67
±6.0 LSB
±2 ppm/°C
70
dB
70
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD
-80 -76
dB
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
SFDR
IMD
fIN1 = 250kHz, fIN2 = 300kHz
-3dB point, small-signal method
S/(N + D) Σ 68dB, single ended
-83 -76
dB
-78 dB
20 MHz
1.2 MHz
Minimum Conversion Time
Maximum Throughput Rate
Minimum Throughput Rate
Track-and-Hold Acquisition Time
Aperture Delay
Aperture Jitter
External Clock Frequency
tCONV (Note 3)
tACQ
(Note 4)
(Note 5)
fSCLK
(Note 6)
0.556
µs
1.8 Msps
10 ksps
104 ns
5 ns
30 ps
28.8 MHz
2 _______________________________________________________________________________________



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1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±5%, VL = VDD, VREF = 4.096V, fSCLK = 28.8MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
ANALOG INPUTS (AIN+, AIN-)
Differential Input Voltage Range
Absolute Input Voltage Range
DC Leakage Current
Input Capacitance
Input Current (Average)
REFERENCE INPUT (REF)
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
AIN+ - AIN-, MAX1274
VIN AIN+ - AIN-, MAX1275
0
-VREF / 2
VREF
+VREF / 2
V
0
VDD
V
±1 µA
Per input pin
16 pF
Time averaged at maximum throughput rate
75
µA
REF Input Voltage Range
VREF
1.0
VDD +
V
50mV
Input Capacitance
DC Leakage Current
Input Current (Average)
DIGITAL INPUTS (SCLK, CNVST)
Input Voltage Low
Input Voltage High
Input Leakage Current
DIGITAL OUTPUT (DOUT)
Output Load Capacitance
Output Voltage Low
Output Voltage High
Output Leakage Current
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
VIL
VIH
IIL
COUT
VOL
VOH
IOL
VDD
VL
Analog Supply Current,
Normal Mode
IDD
Analog Supply Current,
Partial Power-Down Mode
Analog Supply Current,
Full Power-Down Mode
IDD
IDD
Digital Supply Current (Note 7)
Positive-Supply Rejection
PSR
Time averaged at maximum throughput rate
20
±1
400
0.7 x VL
0.05
0.3 x VL
±10
For stated timing performance
ISINK = 5mA, VL 1.8V
ISOURCE = 1mA, VL 1.8V
Output high impedance
VL - 0.5V
±0.2
30
0.4
±10
Static, fSCLK = 28.8MHz
Static, no SCLK
Operational, 1.8Msps
fSCLK = 28.8MHz
No SCLK
fSCLK = 28.8MHz
No SCLK
Operational, full-scale input at 1.8Msps
Static, fSCLK = 28.8MHz
Partial/full power-down mode,
fSCLK = 28.8MHz
Static, no SCLK, all modes
VDD = 5V ±5%, full-scale input
4.75 5.25
1.8 VDD
79
45
9 11
1
1
1
1
1 2.5
0.4 1
0.2 0.5
0.1
±0.2
1
±3.0
pF
µA
µA
V
V
µA
pF
V
V
µA
V
V
mA
mA
µA
mA
µA
mV
_______________________________________________________________________________________ 3



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1.8Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
TIMING CHARACTERISTICS
(VDD = +5V ±5%, VL = VDD, VREF = 4.096V, fSCLK = 28.8MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Rise to DOUT Transition
DOUT Remains Valid After SCLK
CNVST Fall to SCLK Fall
CNVST Pulse Width
Power-Up Time; Full Power-Down
Restart Time; Partial Power-Down
SYMBOL
tCH
tCL
tDOUT
tDHOLD
tSETUP
tCSW
TPWR-UP
tRCV
CONDITIONS
VL = 1.8V to VDD
VL = 1.8V to VDD
CL = 30pF, VL = 4.75V to VDD
CL = 30pF, VL = 2.7V to VDD
CL = 30pF, VL = 1.8V to VDD
VL = 1.8V to VDD
VL = 1.8V to VDD
VL = 1.8V to VDD
MIN
15.6
15.6
4
10
20
TYP
2
16
MAX
14
17
24
UNITS
ns
ns
ns
ns
ns
ns
ms
Cycles
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CNST. The IC idles in acquisition mode between conversions.
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: Digital supply current is measured with the VIH level equal to VL, and the VIL level equal to GND.
CNVST
SCLK
tSETUP
DOUT
tCL tCH
tDHOLD
tDOUT
VL
tCSW
DOUT
6k
DOUT
6kCL
GND
a) HIGH-Z TO VOH, VOL TO VOH,
AND VOH TO HIGH-Z
CL
GND
b) HIGH-Z TO VOL, VOH TO VOL,
AND VOL TO HIGH-Z
Figure 1. Detailed Serial-Interface Timing
Figure 2. Load Circuits for Enable/Disable Times
4 _______________________________________________________________________________________



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