MAX11212 Datasheet PDF - Maxim Integrated Products


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MAX11212
Maxim Integrated Products

Part Number MAX11212
Description Delta- Sigma ADC with 2-Wire Serial Interface
Page 14 Pages

MAX11212 datasheet pdf
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19-5247; Rev 0; 4/10
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18-Bit, Single-Channel, Ultra-Low Power, Delta-
Sigma ADC with 2-Wire Serial Interface
General Description
The MAX11212 is an ultra-low power (< 300FA max
active current), high-resolution, serial-output ADC. This
device provides the highest resolution per unit power
in the industry, and is optimized for applications that
require very high dynamic range with low power such as
sensors on a 4mA to 20mA industrial control loop. The
MAX11212 provides a high-accuracy internal oscillator
that requires no external components.
When used with the specified data rates, the internal
digital filter provides more than 80dB rejection of 50Hz or
60Hz line noise. The MAX11212 provides a simple 2-wire
serial interface in the space-saving, 10-pin FMAXM pack-
age. The MAX11212 operates over the -40NC to +85NC
temperature range.
Applications
Sensor Measurement (Temperature and
Pressure)
Portable Instrumentation
Battery Applications
Weigh Scales
Features
S 18-Bit Full-Scale Resolution
S 720nVRMS Noise (MAX11212B)
S 3ppm INL
S No Missing Codes
S Ultra-Low-Power Dissipation
Operating-Mode Current Drain < 300µA (max)
Sleep-Mode Current Drain < 0.1µA
S 2.7V to 3.6V Analog Supply Voltage Range
S 1.7V to 3.6V Digital and I/O Supply Voltage Range
S Fully Differential Signal Inputs
S Fully Differential Reference Inputs
S Internal System Clock
2.4576MHz (MAX11212A)
2.2528MHz (MAX11212B)
S External Clock
S Serial 2-Wire Interface (Clock Input and Data
Output)
S On-Demand Offset and Gain Self-Calibration
S -40°C to +85°C Operating Temperature Range
S ±2kV ESD Protection
S Lead(Pb)-Free and RoHS-Compliant µMAX
Package
RESOLUTION
(BITS)
4-WIRE SPI, 16-PIN QSOP,
PROGRAMMABLE GAIN
24 MAX11210
20 MAX11206
18 MAX11209
16 MAX11213
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Ordering Information
PART
PIN-PACKAGE
OUTPUT RATE
(sps)
MAX11212AEUB+*
MAX11212BEUB+
10 FMAX
10 FMAX
120
13.75
Note: All devices are specified over the -40°C to +85°C oper-
ating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Future productcontact factory for availability.
4-WIRE SPI,
16-PIN QSOP
MAX11200
MAX11207
MAX11211
MAX11203
Selector Guide
2-WIRE SERIAL,
10-PIN μMAX
MAX11201 (with buffers)
MAX11202 (without buffers)
MAX11208
MAX11212
MAX11205
________________________________________________________________ Maxim Integrated Products   1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.



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18-Bit, Single-Channel, Ultra-Low Power, Delta-
Sigma ADC with 2-Wire Serial Interface
ABSOLUTE MAXIMUM RATINGS
Any Pin to GND.....................................................-0.3V to +3.9V
AVDD to GND.......................................................-0.3V to +3.9V
DVDD to GND.......................................................-0.3V to +3.9V
Analog Inputs (AINP, AINN, REFP, REFN)
to GND ............................................. -0.3V to (VAVDD + 0.3V)
Digital Inputs and Digital Outputs
to GND ............................................. -0.3V to (VDVDD + 0.3V)
ESDHB (AVDD, AINP, AINN, REFP, REFN, DVDD, CLK, SCLK,
RDY/DOUT, GND) ............................................ Q2kV (Note 1)
Continuous Power Dissipation (TA = +70NC)
10-Pin FMAX (derate 5.6mW/NC above +70NC)...........444mW
Operating Temperature Range........................... -40NC to +85NC
Junction Temperature......................................................+150NC
Storage Temperature Range............................ -55NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Note 1: Human Body Model to specification MIL-STD-883 Method 3015.7.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
ADC PERFORMANCE
Noise-Free Resolution
NFR (Notes 2, 3)
18 Bits
Thermal Noise (Notes 2, 3)
VN
MAX11212A
MAX11212B
2.1
0.72
FVRMS
Integral Nonlinearity
INL (Note 4)
-10 +10 ppmFSR
Zero Error
Zero Drift
VOFF After calibration, VREFP - VREFN = 2.5V
-20
1
+20 ppmFSR
50 nV/NC
Full-Scale Error
After calibration, VREFP - VREFN = 2.5V
(Note 5)
-35
3
+35 ppmFSR
Full-Scale Error Drift
Power-Supply Rejection
AVDD DC rejection
DVDD DC rejection
0.05
70 80
90 100
ppmFSR/NC
dB
ANALOG INPUTS/REFERENCE INPUTS
DC rejection
90 123
Common-Mode Rejection
CMR 50Hz/60Hz rejection MAX11212A
90
dB
50Hz/60Hz rejection MAX11212B
144
Normal-Mode 50Hz Rejection
Normal-Mode 60Hz Rejection
Common-Mode Voltage Range
NMR50 MAX11212B (Note 6)
NMR60 MAX11212B (Note 6)
65
73
GND
80.5
87
VAVDD
dB
dB
V
Absolute Input Voltage
Low input voltage
High input voltage
GND -
30mV
VAVDD +
30mV
V
DC Input Leakage
AIN Dynamic Input Current
REF Dynamic Input Current
AIN Input Capacitance
Sleep mode (Note 2)
±1 FA
5 FA
7.5 FA
10 pF
2   _______________________________________________________________________________________



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18-Bit, Single-Channel, Ultra-Low Power, Delta-
Sigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
REF Input Capacitance
15 pF
AIN Voltage Range
VAINP - VAINN
-VREF
+VREF
V
REF Voltage Range
Input Sampling Rate
fS
MAX11212A
MAX11212B
VAVDD
246
225
V
kHz
REF Sampling Rate
MAX11212A
MAX11212B
246
225
kHz
LOGIC INPUTS (SCLK, CLK)
Input Current
Input leakage current
±1 FA
Input Low Voltage
VIL
0.3 x
VDVDD
V
Input High Voltage
Input Hysteresis
External Clock
VIH
VHYS
MAX11212A
MAX11212B
0.7 x
VDVDD
200
2.4576
2.2528
V
mV
MHz
LOGIC OUTPUTS (RDY/DOUT)
Output Low Level
VOL
IOL = 1mA; also tested for VDVDD =
3.6V
0.4 V
Output High Level
Floating State Leakage Current
Floating State Output
Capacitance
VOH
IOH = 1mA; also tested for VDVDD =
3.6V
Output leakage current
0.9 x
VDVDD
±10
9
V
FA
pF
POWER REQUIREMENTS
Analog Supply Voltage
AVDD
Digital Supply Voltage
DVDD
Total Operating Current
AVDD + DVDD
DVDD Operating Current
AVDD Operating Current
AVDD Sleep Current
DVDD Sleep Current
2-WIRE SERIAL-INTERFACE TIMING CHARACTERISITCS
SCLK Frequency
fSCLK
SCLK Pulse Width Low
t1 60/40 duty cycle 5MHz clock
SCLK Pulse Width High
t2 40/60 duty cycle 5MHz clock
SCLK Rising Edge to Data Valid
Transition Time
t3
2.7 3.6
1.7 3.6
230 300
45 60
185 245
0.4 2
0.35
2
5
80
80
40
V
V
FA
FA
FA
FA
FA
MHz
ns
ns
ns
_______________________________________________________________________________________   3



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18-Bit, Single-Channel, Ultra-Low Power, Delta-
Sigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
SCLK Rising Edge Data Hold
Time
t4 Allows for positive edge data read
3
ns
RDY/DOUT Fall to SCLK Rising
Edge
t5
Next Data Update Time; No Read
Allowed
t6
MAX11212A
MAX11212B
Data Conversion Time
t7
MAX11212A
MAX11212B
Data Ready Time After Calibration
Starts (CAL + CNV)
t8
MAX11212A
MAX11212B
SCLK High After RDY/DOUT
Goes Low to Activate Sleep Mode
t9
MAX11212A
MAX11212B
0
155
169
8.6
73
208.3
256.1
0 8.6
0 73
ns
Fs
ms
ms
ms
Time From RDY/DOUT Low
to SCLK High for Sleep Mode
Activation
MAX11212A
t10
MAX11212B
0 8.6
ms
0 73
Data Ready Time After Wake-Up
from Sleep Mode
t11
MAX11212A
MAX11212B
Data Ready Time After Calibration
MAX11212A
from Sleep Mode Wake-Up (CAL
t12
+ CNV)
MAX11212B
8.6
73
208.4
256.2
ms
ms
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: VAINP = VAINN.
Note 4: ppmFSR is parts per million of full-scale range.
Note 5: Positive full-scale error includes zero-scale errors.
4   _______________________________________________________________________________________




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