M-88L70-01P Datasheet PDF - Clare Inc.

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M-88L70-01P
Clare Inc.

Part Number M-88L70-01P
Description 3V DTMF Receiver
Page 8 Pages


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M-88L70
3V DTMF Receiver
Features
Operates between 2.7 and 3.6 volts
Low power consumption
Power-down mode
Inhibit mode
Central office quality and performance
Inexpensive 3.58 MHz time base
Adjustable acquisition and release times
Dial tone suppression
Functionally compatible with Clare’s M-8870
Applications
Telephone switch equipment
Mobile radio
Remote control
Paging systems
PCMCIA
Portable TAD
Remote data entry
Description
The M-88L70 monolithic DTMF receiver offers small size,
low power consumption and high performance, with 3 volt
operation. Its architecture consists of a bandsplit filter
section, which separates the high and low group tones,
followed by a digital counting section which verifies the
frequency and duration of the received tones before
passing the corresponding code to the output bus.
Ordering Information
Part #
M-88L70-01P
M-88L70-01S
M-88L70-01T
Description
18-pin plastic DIP
18-pin SOIC
18-pin SOIC, Tape and Reel
Figure 1 Pin Connections
The M-88L70 is a full DTMF Receiver that integrates
both bandsplit filter and decoder functions into a single
18-pin DIP or SOIC package. Manufactured using
CMOS process technology, the M-88L70 offers low
power consumption (18 mW max), precise data handling
and 3V operation. Its filter section uses switched capaci-
tor technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting
techniques to detect and decode all 16 DTMF tone pairs
into a 4-bit code. External component count is minimized
by provision of an on-chip differential input amplifier,
clock generator, and latched tri-state interface bus.
Minimal external components required include a low-cost
3.579545 MHz color burst crystal, a timing resistor, and a
timing capacitor.
Figure 2 Block Diagram
DS-M88L70-R1
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M-88L70
Filter
The low and high group tones are separated by applying
the dual-tone signal to the inputs of two 9th order
switched capacitor bandpass filters with bandwidths that
correspond to the bands enclosing the low and high
group tones. The filter also incorporates notches at 350
and 440 Hz, providing excellent dial tone rejection. Each
filter output is followed by a single-order switched capac-
itor section that smoothes the signals prior to limiting.
Signal limiting is performed by high-gain comparators
provided with hysteresis to prevent detection of unwant-
ed low-level signals and noise. The comparator outputs
provide full-rail logic swings at the frequencies of the
incoming tones.
Decoder
The M-88L70 decoder uses a digital counting technique
to determine the frequencies of the limited tones and to
verify that they correspond to standard DTMF frequen-
cies. A complex averaging algorithm is used to protect
against tone simulation by extraneous signals (such as
voice) while tolerating small frequency variations. The
algorithm ensures an optimum combination of immunity
to talkoff and tolerance to interfering signals (third tones)
and noise. When the detector recognizes the simultane-
ous presence of two valid tones (known as “signal condi-
tion”), it raises the Early Steering flag (ESt). Any subse-
quent loss of signal condition will cause ESt to fall.
Steering Circuit
Before a decoded tone pair is registered, the receiver
checks for a valid signal duration (referred to as “char-
acter-recognition-condition”). This check is performed
by an external RC time constant driven by ESt. A logic
high on ESt causes VC (see Figure 3) to rise as the
capacitor discharges. Provided that signal condition is
maintained (ESt remains high) for the validation period
(tGTP), VC reaches the threshold (VTSt) of the steering
logic to register the tone pair, thus latching its corre-
sponding 4-bit code (see Table 2) into the output latch.
At this point, the GT output is activated and drives VC to
VDD. GT continues to drive high as long as ESt remains
high. Finally, after a short delay to allow the output latch
to settle, the “delayed steering” output flag (StD) goes
high, signaling that a received tone pair has been reg-
istered. The contents of the output latch are made
available on the 4-bit output bus by raising the three-
state control input (OE) to a logic high. The steering cir-
cuit works in reverse to validate the interdigit pause
between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate
signal interruptions (dropouts) too short to be consid-
Table 1 Pin Functions
Pin
1
2
3
4
5
6
7
8
9
10
11-14
15
Name
IN+
IN
GS
VREF
INH
PD
OSC1
OSC2
VSS
OE
Q1, Q2,
Q3, Q4
StD
16 ESt
17 St/GT
18 VDD
Description
Non-inverting input
-Inverting input
Connections to the front-end differential amplifier
Gain select. Gives access to output of front-end amplifier for connection of feedback resistor.
Reference voltage output (nominally VDD/2). May be used to bias the inputs at mid-rail.
Inhibits detection of tones representing keys A, B, C, and D. This input is internally pulled down.
Power down. Logic high powers down the device and inhibits the oscillator. This input is internally pulled down.
Clock input
Clock output
3.579545 MHz crystal connected between these pins completes internal oscillator.
Negative power supply (normally connected to 0 V).
Tri-state output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup.
Tri-state outputs. When enabled by OE, provides the code corresponding to the last valid tone pair received
(see Table 5.)
Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is
updated. Returns to logic low when the voltage on St/GT falls below VTSt
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair
(signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to
register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new
tone pair. The GT output acts to reset the external steering time constant, and its state is a function of ESt and the
voltage on St. (See Figure 5).
Positive power supply
2
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M-88L70
ered a valid pause. This capability, together with the
ability to select the steering time constants externally,
allows the designer to tailor performance to meet a wide
variety of system requirements.
Figure 3 Basic Steering Circuit
Guard Time Adjustment
Where independent selection of receive and pause are
not required, the simple steering circuit of Figure 3 is
applicable. Component values are chosen according to
the formula:
tREC = tDP + tGTP
tGTP @ 0.67 RC
The value of tDP is a parameter of the device and tREC is
the minimum signal duration to be recognized by the
receiver. A value for C of 0.1 µF is recommended for
most applications, leaving R to be selected by the
designer. For example, a suitable value of R for a tREC of
40 ms would be 300 K ohm. A typical circuit using this
steering configuration is shown in Figure 4. The timing
requirements for most telecommunication applications
are satisfied with this circuit. Different steering arrange-
ments may be used to select independently the guard
times for tone-present (tGTP) and tone-absent (tGTA). This
may be necessary to meet system specifications that
place both accept and reject limits on both tone duration
and interdigit pause.
Guard time adjustment also allows the designer to tailor
system parameters such as talkoff and noise immunity.
Increasing tREC improves talkoff performance, since it
reduces the probability that tones simulated by speech
will maintain signal condition long enough to be regis-
tered. On the other hand, a relatively short tREC with a
long tDO would be appropriate for extremely noisy envi-
ronments where fast acquisition time and immunity to
dropouts would be required. Design information for
guard time adjustment is shown in Figure 5.
Input Configuration
The input arrangement of the M-88L70 provides a dif-
ferential input operational amplifier as well as a bias
source (VREF) to bias the inputs at mid-rail. Provision is
made for connection of a feedback resistor to the op-
amp output (GS) for gain adjustment.
In a single-ended configuration, the input pins are con-
nected as shown in Figure 4 with the op-amp connect-
ed for unity gain and VREF biasing the input at 1/2VDD.
Figure 7 shows the differential configuration, which per-
mits gain adjustment with the feedback resistor R5.
Table 2 Tone Decoding
FLOW FHIGH Key OE INH ESt Q4 Q3 Q2 Q1
(ref.)
ANY ANY ANY L X H Z Z Z Z
697 1209 1 H X H 0 0 0 1
697 1336 2 H X H 0 0 1 0
697 1477 3 H X H 0 0 1 1
770 1209 4 H X H 0 1 0 0
770 1336 5 H X H 0 1 0 1
770 1477 6 H X H 0 1 1 0
852 1209 7 H X H 0 1 1 1
852 1336 8 H X H 1 0 0 0
852 1477 9 H X H 1 0 0 1
941 1336 0 H X H 1 0 1 0
941 1209 * H X H 1 0 1 1
941 1477 # H X H 1 1 0 0
697 1633 A H L H 1 1 0 1
770 1633 B H L H 1 1 1 0
852 1633 C H L H 1 1 1 1
941 1633 D H L H 0 0 0 0
697 1633
770 1633
852 1633
941 1633
A
B
C
D
HH
HH
HH
DH
L Undetected, the output
L code will remain the
L same as the previous
L detected code.
L = logic low, H = logic high, Z = high impedance, X = don’t care
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M-88L70
Absolute Maximum Ratings
Parameter
Symbol
Value
Power supply voltage
(VDD - VSS)
VDD 6.0 V max
Voltage on any pin
Vdc VSS -0.3 Min,
VDD +0.3 Max
Current on any pin
IDD 10 mA max
Operating temperature
TA -40˚C to + 85˚C
Storage temperature
TS -65˚C to + 150˚C
Note:
Exceeding these ratings may cause permanent damage. Functional operation under these condi-
tions is not implied.
Absolute Maximum Ratings are stress ratings. Stresses
in excess of these ratings can cause permanent dam-
age to the device. Functional operation of the device at
these or any other conditions beyond those indicated in
the operational sections of this data sheet is not implied.
Exposure of the device to the absolute maximum ratings
for an extended period may degrade the device and
effect its reliability.
Table 4 DC Characteristics
PARAMETER
SYMBOL MIN TYP MAX
Operating supply voltage
VDD 2.7 3.0
Operating supply current
IDD - 3.0
Standby supply current
IDDS - 5.0
Power consumption
PO - 9
Low level input voltage
VIL -v -
High level input voltage
VIH 2 -
Input leakage current
IIH/IIL
- 0.1
Pullup (source) current on OE
ISO -12 -
Pull down (sink) Curent PD
IPD - 1.0
Pull down (sink) Current INH
IINH - 1.0
Input impedance, signal inputs 1, 2
RIN
- 10
Steering threshold voltage
VTSt - 1.5
Low level output voltage
VOL - 0.1
High level output voltage
VOH 2.4 2.6
Output high (source) current
IOH 1.0
Output voltage VREF
VREF - 1.5
Output resistance VREF
ROR - 10
Notes:
1. All voltages referenced to VSS unless otherwise noted. For typical values, VDD = 3.0 V + 20%/-10%, VSS = 0 V, TA = 25˚C
2. Input pins defined as IN+, IN-, and OE.
3.6
5.0
10
18
1.0
-
-
-
45
45
-
-
0.4
-
-
-
-
UNITS
V
mA
µA
mW
V
V
µA
µA
µA
µA
M
V
V
V
mA
V
k
TEST CONDITIONS
PD=VDD
VDD = 3.0 V
VDD = 3.0 V
VIN = VSS or VDD (see Note 2)
OE = 0 V
PD = 3.0 V
INH = 3.0 V
@ 1 kHz
IOL = 1.0 mA
IOH = -400 mA
VOUT = 2.5 V @ VDD = 2.7 V
No load
4
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M-88L70-01P datasheet pdf
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