M-8870 Datasheet PDF - Clare

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M-8870
Clare

Part Number M-8870
Description DTMF Receiver
Page 9 Pages


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M-8870 DTMF Receiver
Low power consumption
· Adjustable acquisition and release times
· Central office quality and performance
· Power-down and inhibit modes (-02 only)
· Inexpensive 3.58 MHz time base
· Single 5 volt power supply
· Dial tone suppression
·· Applications include: telephone switch equipment,
remote data entry, paging systems, personal
computers, credit card systems
The M-8870 is a full DTMF Receiver that integrates both
bandsplit filter and decoder functions into a single 18-pin DIP
or SOIC package. Manufactured using CMOS process tech-
nology, the M-8870 offers low power consumption (35 mW max)
and precise data handling. Its filter section uses switched ca-
pacitor technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting tech-
niques to detect and decode all 16 DTMF tone pairs into a 4-
bit code. External component count is minimized by provision
of an on-chip differential input amplifier, clock generator, and
latched tri-state interface bus. Minimal external components
required include a low-cost 3.579545 MHz color burst crystal,
a timing resistor, and a timing capacitor.
Figure 1 Pin Connections
The M-8870-02 provides a “power-down” option which, when
enabled, drops consumption to less than 0.5 mW.The M-8870-
02 can also inhibit the decoding of fourth column digits (see
Table 5).
40-406-00011, Rev. F
Figure 2 Block Diagram
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M-8870
Functional Description
M-8870 operating functions (see Figure 2) include a bandsplit
filter that separates the high and low tones of the received pair,
and a digital decoder that verifies both the frequency and dura-
tion of the received tones before passing the resulting 4-bit code
to the output bus.
Filter
The low and high group tones are separated by applying the
dual-tone signal to the inputs of two 6th order switched capacitor
bandpass filters with bandwidths that correspond to the bands
enclosing the low and high group tones. The filter also incorpo-
rates notches at 350 and 440 Hz, providing excellent dial tone
rejection. Each filter output is followed by a single-order
switched capacitor section that smooths the signals prior to lim-
iting. Signal limiting is performed by high-gain comparators pro-
vided with hysteresis to prevent detection of unwanted low-level
signals and noise. The comparator outputs provide full-rail logic
swings at the frequencies of the incoming tones.
Decoder
The M-8870 decoder uses a digital counting technique to deter-
mine the frequencies of the limited tones and to verify that they
correspond to standard DTMF frequencies. A complex averag-
ing algorithm is used to protect against tone simulation by extra-
neous signals (such as voice) while tolerating small frequency
variations. The algorithm ensures an optimum combination of
immunity to talkoff and tolerance to interfering signals (third
tones) and noise. When the detector recognizes the simulta-
neous presence of two valid tones (known as “signal condition”),
it raises the Early Steering flag (ESt). Any subsequent loss of
signal condition will cause ESt to fall.
Steering Circuit
Before a decoded tone pair is registered, the receiver checks for
a valid signal duration (referred to as “charac-
ter-recognition-condition”). This check is performed by an exter-
nal RC time constant driven by ESt. A logic high on ESt causes
VC (see Figure 2) to rise as the capacitor discharges. Provided
that signal condition is maintained (ESt remains high) for the val-
idation period (tGTF), VC reaches the threshold (VTSt) of the
steering logic to register the tone pair, thus latching its corre-
sponding 4-bit code (see Table 3) into the output latch. At this
point, the GT output is activated and drives VC to VDD. GT con-
tinues to drive high as long as ESt remains high. Finally, after a
Figure 3 Basic Steering Circuit
short delay to allow the output latch to settle, the “delayed steer-
ing” output flag (StD) goes high, signaling that a received tone
pair has been registered. The contents of the output latch are
made available on the 4-bit output bus by raising the three-state
control input (OE) to a logic high. The steering circuit works in re-
verse to validate the interdigit pause between signals. Thus, as
well as rejecting signals too short to be considered valid, the re-
ceiver will tolerate signal interruptions (dropouts) too short to be
considered a valid pause. This capability, together with the abil-
ity to select the steering time constants externally, allows the de-
signer to tailor performance to meet a wide variety of system
requirements.
Figure 4 Single-Ended Input Configuration
Guard Time Adjustment
Where independent selection of signal duration and interdigit
pause are not required, the simple steering circuit of Figure 3 is
applicable. Component values are chosen according to the for-
mula:
tREC = tDP + tGTP
tGTP 0.67 RC
The value of tDP is a parameter of the device and tREC is the mini-
mum signal duration to be recognized by the receiver. A value
for C of 0.1 µF is recommended for most applications, leaving R
to be selected by the designer. For example, a suitable value of
R for a tREC of 40 ms would be 300 k. A typical circuit using this
steering configuration is shown in Figure 4. The timing require-
ments for most telecommunication applications are satisfied
with this circuit. Different steering arrangements may be used to
select independently the guard times for tone-present (tGTP) and
tone-absent (tGTA). This may be necessary to meet system
specifications that place both accept and reject limits on both
tone duration and interdigit pause.
40-406-00011, Rev. F
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M-8870
Table 1 Pin Functions
Pin Name
Description
1 IN+ Non-inverting input Connections to the front-end differential amplifier.
2 IN- Inverting input
3 GS Gain select. Gives access to output of front-end amplifier for connection of feedback resistor.
4 VREF Reference voltage output (nominally VDD/2). May be used to bias the inputs at mid-rail.
5 INH* Inhibits detection of tones representing keys A, B, C, and D.
6 PD* Power down. Logic high powers down the device and inhibits the oscillator. Internal pulldown.
7 OSC1 Clock input
3.579545 MHz crystal connected between these pins completes the internal oscillator.
8 OSC2 Clock output
9 VSS Negative power supply (normally connected to 0 V).
10 OE Tri-statable output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup.
11 - 14 Q1, Q2, Tri-statable data outputs. When enabled by OE, provides the code corresponding to the last valid tone pair received (see
Q3, Q4 Table 5).
15 StD Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is up-
dated. Returns to logic low when the voltage on St/GT falls below VTSt.
16 ESt Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (sig-
nal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
17 St/GT Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register
the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair.
The GT output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St.
(See Figure 7).
18 VDD Positive power supply. (Normally connected to +5V.)
* -02 only. Connect to VSS for -01 version
Guard time adjustment also allows the designer to tailor system
parameters such as talkoff and noise immunity. Increasing tREC
improves talkoff performance, since it reduces the probability
that tones simulated by speech will maintain signal condition
long enough to be registered. On the other hand, a relatively
short tREC with a long tDO would be appropriate for extremely
noisy environments where fast acquisition time and immunity to
dropouts would be required. Design information for guard time
adjustment is shown in Figure 5.
Power-down and Inhibit Mode ( -02 only)
A logic high applied to pin 6 (PD) will place the device into
standby mode to minimize power consumption. It stops the os-
cillator and the functioning of the filters. On the M-8870-01 mod-
els, this pin is tied to ground (logic low).
Inhibit mode is enabled by a logic high input to pin 5 (INH). It in-
hibits the detection of 1633 Hz. The output code will remain the
same as the previous detected code (see Table 1). On the
M-8870-01 models, this pin is tied to ground (logic low).
Input Configuration
The input arrangement of the M-8870 provides a differential in-
put operational amplifier as well as a bias source (VREF) to bias
the inputs at mid-rail. Provision is made for connection of a feed-
back resistor to the op-amp output (GS) for gain adjustment.
In a single-ended configuration, the input pins are connected as
shown in Figure 4 with the op-amp connected for unity gain and
VREF biasing the input at 1/2VDD. Figure 6 shows the differential
configuration, which permits gain adjustment with the feedback
resistor R5.
DTMF Clock Circuit
The internal clock circuit is completed with the addition of a stan-
dard 3.579545 MHz television color burst crystal. The crystal
can be connected to a single M-8870 as shown in Figure 4, or to
a series of M-8870s. As illustrated in Figure 7, a single crystal
can be used to connect a series of M-8870s by coupling the os-
cillator output of each M-8870 through a 30 pF capacitor to the
oscillator input of the next M-8870.
Figure 5 Guard Time Adjustment
40-406-00011, Rev. F
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M-8870
Table 2 Absolute Maximum Ratings
Parameter
Symbol
Value
Power supply voltage (VDD - VSS)
Voltage on any pin
Current on any pin
Operating temperature
Storage temperature
VDD
VDC
IDD
TA
TS
6.0 V max
VSS -0.3, VDD +0.3
10 mA max
-40°C to + 85°C
-65°C to + 150°C
Note:
Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied.
Parameter
Operating supply voltage
Operating supply current
Standby supply current (see Note 3)
Power consumption
Low level input voltage
High level input voltage
Input leakage current
Pullup (source) current on OE
Input impedance, signal inputs 1, 2
Steering threshold voltage
Low level output voltage
High level output voltage
Output low (sink) current
Output high (source) current
Output voltage VREF
Output resistance VREF
Table 3 DC Characteristics
Symbol
VDD
IDD
IDDQ
PO
VIL
VIH
IIH/IIL
ISO
RIN
VTSt
VOL
VOH
IOL
IOH
VREF
ROR
Min
4.75
3.5
8
2.2
VDD - 0.03
1.0
0.4
2.4
Typ*
3.0
15
0.1
6.5
10
2.5
0.8
10
Max
5.25
7.0
100
35
1.5
15.0
2.5
0.03
2.7
Units
V
mA
µA
mW
V
V
µA
µA
m
V
V
V
mA
mA
V
k
Test Conditions
PD=VDD
f = 3.579 MHz, VDD = 5.0 V
VIN = VSS or VDD (see Note 2)
OE = 0 V
@ 1 kHz
No load
No load
VOUT = 0.4 V
VOUT = VDD - 0.4 V
No load
Table 4 Operating Characteristics - Gain Setting Amplifier
Parameter
Symbol
Min
Typ*
Max
Units
Input leakage current
Input resistance
Input offset voltage
Power supply rejection
IN
RIN
VOS
PSRR
± 100
4
± 25
50
nA
M
mV
dB
Common mode rejection
CMRR
55
dB
DC open loop voltage gain
AVOL
60
dB
Open loop unity gain bandwidth
fC
1.2 1.5
MHz
Output voltage swing
VO 3.5
VP-P
Tolerable capacitive load (GS)
CL
100 pF
Tolerable resistive load (GS)
RL
50 k
Common mode range
VCM
2.5
V P-P
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Note:
1. All voltages referenced to VSS unless otherwise noted. For typical values VDD = 5.0 V, VSS = 0 V, TA = 25°C.
Test Conditions
VSS < VIN < VDD
1 KHz
-3.0V < VIN < 3.0V
RL 100 Kto VSS
No load
40-406-00011, Rev. F
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