ELECTRICAL CHARACTERISTICS The q denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, SHDN = 12V, BOOST = 15.3V, BIAS = 5V, FB/PGFB = 1.25V,
CSS/SYNC = 0V unless otherwise noted.
MIN TYP MAX UNITS
Switch On Resistance (Note 9)
q 180 200 230
Maximum Duty Cycle
Minimum SYNC Amplitude
SYNC Frequency Range
SYNC Input Impedance
CSS Current Threshold (Note 10)
PGFB Input Current
PGFB Voltage Threshold (Note 11)
CT Source Current (Note 11)
CT Sink Current (Note 11)
CT Voltage Threshold (Note 11)
PG Leakage (Note 11)
10 13 16
q 88 90 92
1.16 1.2 1.24
PG Sink Current (Note 11)
PGFB = 1V, PG = 400mV
Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.
Note 2: The LT1976EFE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT1976IFE is guaranteed and tested over the full –40°C to 125°C operating
junction temperature range.
Note 3: Minimum input voltage is defined as the voltage where switching
starts. Actual minimum input voltage to maintain a regulated output will
depend upon output voltage and load current. See Applications Information.
Note 4: Supply input current is the quiescent current drawn by the input
pin. Its typical value depends on the voltage on the BIAS pin and operating
state of the LT1976. With the BIAS pin at 0V, all of the quiescent current
required to operate the LT1976 will be provided by the VIN pin. With the
BIAS voltage above its minimum input voltage, a portion of the total
quiescent current will be supplied by the BIAS pin. Supply sleep current is
defined as the quiescent current during the “sleep” portion of Burst Mode
operation. See Applications Information for determining application supply
Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when IBIAS is
sourced into the pin.
Note 6: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 7: Boost current is the current flowing into the BOOST pin with the pin
held 3.3V above input voltage. It flows only during switch on time.
Note 8: Gain is measured with a VC swing from 1.15V to 750mV.
Note 9: Switch on resistance is calculated by dividing VIN to SW voltage by the
forced current (1.5A). See Typical Performance Characteristics for the graph
of switch voltage at other currents.
Note 10: The CSS threshold is defined as the value of current sourced into the
CSS pin which results in an increase in sink current from the VC pin. See the
Soft-Start section in Applications Information.
Note 11: The PGFB threshold is defined as the percentage of VREF voltage
which causes the current source output of the CT pin to change from
sinking (below threshold) to sourcing current (above threshold). When
sourcing current, the voltage on the CT pin rises until it is clamped
internally. When the clamp is activated, the output of the PG pin will be set
to a high impedance state. When the CT clamp is inactive the PG pin will
be set active low with a current sink capability of 200µA.