LPC2157 Datasheet PDF - NXP Semiconductors

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LPC2157
NXP Semiconductors

Part Number LPC2157
Description Single-chip 16-bit/32-bit microcontrollers; 512 kB fash
Page 30 Pages


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LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers; 512 kB flash, with
32 segment x 4 LCD driver
Rev. 02 — 9 February 2009
Product data sheet
1. General description
The LPC2157/2158 is a multi-chip module consisting of a LPC2138/2148 single-chip
microcontroller combined with a PCF8576D Universal LCD driver in a low-cost 100-pin
package. The LCD driver provides 32 segments and supports from 1 to 4 backplanes.
Display overhead is minimized by an on-chip display RAM with auto-increment
addressing. Refer to the respective LPC2148 and LPC2138 user manual for details.
2. Features
I 128-bit wide interface/accelerator enables high-speed 60 MHz operation.
N 32 kB to 40 kB of on-chip static RAM and 512 kB of on-chip flash memory.
I USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM.
N An additional 8 kB of on-chip RAM accessible to USB by DMA (LPC2158 only).
I 32 segment × 4 backplane LCD controller supports from 1 to 4 backplanes.
I Single 10-bit DAC provides variable analog output.
I Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input.
I Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s),
SPI and SSP with buffering and variable data length capabilities.
I Single power supply chip with POR and BOD circuits:
N CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant
I/O pads.
I 100-pin LQFP package with 38 microcontroller I/O pins minimum.
I Individual enable/disable of peripheral functions as well as peripheral clock scaling for
additional power optimization.
3. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
LPC2157FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm
LPC2158FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm
Version
SOT407-1
SOT407-1



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4. Block diagram
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LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
P1[31:25],
P1[17:16]
P0[31:28], P0[27:26](1),
P0[25], P0[23:0]
LPC2157/
LPC2158
MCU
PCF8576D
LCD
CONTROLLER
S[31:0]
BP[3:0]
VLCD
002aad382
(1) LPC2157 only.
Fig 1. Block diagram of LPC2157/2158
LPC2157_2158_2
Product data sheet
Rev. 02 — 9 February 2009
© NXP B.V. 2009. All rights reserved.
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LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
TMS(1) TDI(1)
TRST(1) TCK(1) TDO(1)
XTAL2
XTAL1 RESET
P1[31:25],
P1[17:16]
P0[31:28],
P0[27:26](3)
P0[25],
P0[23:0]
LPC2157/2158
FAST GENERAL
PURPOSE I/O
ARM7 local bus
TEST/DEBUG
INTERFACE
ARM7TDMI-S
AHB BRIDGE
INTERNAL
SRAM
CONTROLLER
INTERNAL
FLASH
CONTROLLER
PLL0
system
clock
PLL1
SYSTEM
FUNCTIONS
USB
clock
VECTORED
INTERRUPT
CONTROLLER
AMBA AHB
(Advanced High-performance Bus)
EINT3 to
EINT0
4 × CAP0
4 × CAP1
8 × MAT0
8 × MAT1
AD0[7:6],
AD0[5](3)
AD0[0](3)
AD0[4:1]
AD1[7:0]
AOUT
P0[31:28] and
P0[25:0]
P1[31:16]
PWM[6:1]
32 kB
SRAM
512 kB
FLASH
EXTERNAL
INTERRUPTS
CAPTURE/COMPARE
(W/EXTERNAL CLOCK)
TIMER 0/TIMER 1
A/D CONVERTERS
0 AND 1
D/A CONVERTER
GENERAL
PURPOSE I/O
PWM0
AHB TO APB APB
BRIDGE DIVIDER
8 kB RAM
SHARED WITH
USB DMA(2)
AHB
DECODER
APB (advanced
peripheral bus)
USB 2.0 FULL-SPEED
DEVICE CONTROLLER
WITH DMA(2)
I2C-BUS SERIAL
INTERFACES 0 AND 1
SPI AND SSP
SERIAL INTERFACES
UART0/UART1
REAL-TIME CLOCK
WATCHDOG
TIMER
D+
D
UP_LED
CONNECT
VBUS
SCL0, SCL1
SDA0, SDA1
SCK0, SCK1
MOSI0, MOSI1
MISO0, MISO1
SSEL0, SSEL1
TXD0, TXD1
RXD0, RXD1
DSR1,CTS1,
RTS1, DTR1,
DCD1,RI1
RTCX1
RTCX2
VBAT
SYSTEM
CONTROL
002aad384
(1) Pins shared with GPIO.
(2) USB DMA controller with 8 kB of RAM accessible as general purpose RAM and/or DMA is available in LPC2158 only.
(3) LPC2157 only.
Fig 2. Microcontroller section block diagram
LPC2157_2158_2
Product data sheet
Rev. 02 — 9 February 2009
© NXP B.V. 2009. All rights reserved.
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LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
VDD(LCD)
VLCD
CLK
SYNC
OSC
VSS
SCL_LCD
SDA_LCD
BP0 BP1 BP2 BP3
S[31:0]
LCD BIAS
GENERATOR
LCD
VOLTAGE
SELECTOR
BACKPLANE
OUTPUTS
TIMING
OSCILLATOR
INPUT
FILTERS
BLINKER
POWER-
ON
RESET
DISPLAY
CONTROLLER
COMMAND
DECODER
I2C-BUS
CONTROLLER
DISPLAY SEGMENT OUTPUTS
DISPLAY LATCH
SHIFT REGISTER
INPUT
BANK
SELECTOR
DISPLAY
RAM
40 × 4 BITS
OUTPUT
BANK
SELECTOR
DATA
POINTER
SUB-
ADDRESS
COUNTER
SA0
Fig 3. LCD display controller block diagram
5. Pinning information
5.1 Pinning
A0 A1 A2
002aad449
1 75
LPC2157FBD
25
Fig 4. Pin configuration for LPC2157
51
002aad385
LPC2157_2158_2
Product data sheet
Rev. 02 — 9 February 2009
© NXP B.V. 2009. All rights reserved.
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