LPC2114 Datasheet PDF - NXP Semiconductors

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LPC2114
NXP Semiconductors

Part Number LPC2114
Description Single-chip 16/32-bit microcontrollers; 128/256 kB ISP/IAP fash
Page 30 Pages


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LPC2114/2124
Single-chip 16/32-bit microcontrollers; 128/256 kB ISP/IAP
flash with 10-bit ADC
Rev. 06 — 10 December 2007
Product data sheet
1. General description
The LPC2114/2124 are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation
and embedded trace support, together with 128/256 kB of embedded high-speed flash
memory. A 128-bit wide memory interface and a unique accelerator architecture enable
32-bit code execution at maximum clock rate. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.
With their compact 64-pin package, low power consumption, various 32-bit timers,
4-channel 10-bit ADC, PWM channels and 46 fast GPIO lines with up to nine external
interrupt pins these microcontrollers are particularly suitable for industrial control, medical
systems, access control and point-of-sale. With a wide range of serial communications
interfaces, they are also very well suited for communication gateways, protocol converters
and embedded soft modems as well as many other general-purpose applications.
Remark: Throughout the data sheet, the term LPC2114/2124 will apply to devices with
and without the /00 or /01 suffixes. The /00 or the /01 suffix will be used to differentiate
from other devices only when necessary.
2. Features
2.1 Key features brought by LPC2114/2124/01 devices
I Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device.
They also allow for a port pin to be read at any time regardless of its function.
I Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are
5 V tolerant when configured for digital I/O function(s).
I UART0/1 include fractional baud rate generator, auto-bauding capabilities and
handshake flow-control fully implemented in hardware.
I Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
I SPI programmable data length and master mode enhancement.
I Diversified Code Read Protection (CRP) enables different security levels to be
implemented. This feature is available in LPC2114/2124/00 devices as well.
I General purpose timers can operate as external event counters.
2.2 Key features common for all devices
I 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
I 16 kB on-chip static RAM.



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LPC2114/2124
Single-chip 16/32-bit microcontrollers
I 128/256 kB on-chip flash program memory. 128-bit wide interface/accelerator enables
high speed 60 MHz operation.
I In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or
full chip erase takes 400 ms.
I EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service
routines can continue to execute whilst the foreground task is debugged with the
on-chip RealMonitor software.
I Embedded Trace Macrocell (ETM) enables non-intrusive high speed real-time tracing
of instruction execution.
I Four-channel 10-bit ADC with conversion time as low as 2.44 µs.
I Two 32-bit timers (with four capture and four compare channels), PWM unit (six
outputs), Real-Time Clock (RTC) and watchdog.
I Multiple serial interfaces including two UARTs (16C550), Fast I2C-bus (400 kbit/s) and
two SPIs.
I 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked
Loop with settling time of 100 µs.
I Vectored Interrupt Controller with configurable priorities and vector addresses.
I Up to forty-six 5 V tolerant general purpose I/O pins. Up to nine edge or level sensitive
external interrupt pins available.
I On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
I Two low power modes, Idle and Power-down.
I Processor wake-up from Power-down mode via external interrupt.
I Individual enable/disable of peripheral functions for power optimization.
I Dual power supply:
N CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ± 0.15 V).
N I/O power supply range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.
16/32-bit ARM7TDMI-S processor.
3. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
LPC2114FBD64
LQFP64
plastic low profile quad flat package; 64 leads;
body 10 × 10 × 1.4 mm
LPC2114FBD64/00 LQFP64
plastic low profile quad flat package; 64 leads;
body 10 × 10 × 1.4 mm
LPC2114FBD64/01 LQFP64
plastic low profile quad flat package; 64 leads;
body 10 × 10 × 1.4 mm
LPC2124FBD64
LQFP64
plastic low profile quad flat package; 64 leads;
body 10 × 10 × 1.4 mm
LPC2124FBD64/00 LQFP64
plastic low profile quad flat package; 64 leads;
body 10 × 10 × 1.4 mm
LPC2124FBD64/01 LQFP64
plastic low profile quad flat package; 64 leads;
body 10 × 10 × 1.4 mm
Version
SOT314-2
SOT314-2
SOT314-2
SOT314-2
SOT314-2
SOT314-2
LPC2114_2124_6
Product data sheet
Rev. 06 — 10 December 2007
© NXP B.V. 2007. All rights reserved.
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3.1 Ordering options
Table 2. Ordering options
Type number
Flash RAM
memory
LPC2114FBD64
LPC2114FBD64/00
LPC2114FBD64/01
LPC2124FBD64
LPC2124FBD64/00
LPC2124FBD64/01
128 kB
128 kB
128 kB
256 kB
256 kB
256 kB
16 kB
16 kB
16 kB
16 kB
16 kB
16 kB
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LPC2114/2124
Single-chip 16/32-bit microcontrollers
Fast GPIO/SSP/
Enhanced
UART, ADC,
Timer
no
no
yes
no
no
yes
Temperature range
40 °C to +85 °C
40 °C to +85 °C
40 °C to +85 °C
40 °C to +85 °C
40 °C to +85 °C
40 °C to +85 °C
LPC2114_2124_6
Product data sheet
Rev. 06 — 10 December 2007
© NXP B.V. 2007. All rights reserved.
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4. Block diagram
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LPC2114/2124
Single-chip 16/32-bit microcontrollers
TMS(2) TDI(2) RTCK(2)
TRST(2) TCK(2) TDO(2)
XTAL2
XTAL1 RESET
P0[30:27],
P0[25:0]
P1[31:16]
LPC2114
LPC2124
HIGH-SPEED
GPIO(3)
46 PINS TOTAL
ARM7 LOCAL BUS
TEST/DEBUG
INTERFACE
ARM7TDMI-S
AHB BRIDGE
PLL
system
clock
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
AMBA Advanced High-performance
Bus (AHB)
INTERNAL
SRAM
CONTROLLER
MEMORY
ACCELERATOR
16 kB
SRAM
128/256 kB
FLASH
AHB TO APB APB
BRIDGE DIVIDER
AHB
DECODER
EINT[3:0](1)
4 × CAP0(1)
4 × CAP1(1)
4 × MAT0(1)
4 × MAT1(1)
AIN[3:0](1)
P0[30:27],
P0[25:0]
P1[31:16]
PWM[6:1](1)
EXTERNAL
INTERRUPTS
CAPTURE/
COMPARE
TIMER 0/TIMER 1
A/D CONVERTER
GENERAL
PURPOSE I/O
PWM0
REAL-TIME CLOCK
I2C-BUS SERIAL
INTERFACE
SPI0
SERIAL INTERFACE
SPI1/SSP(3)
SERIAL INTERFACE
UART0/UART1
WATCHDOG
TIMER
SYSTEM
CONTROL
SCL(1)
SDA(1)
SCK0(1)
MOSI0(1)
MISO0(1)
SSEL0(1)
SCK1(1)
MOSI1(1)
MISO1(1)
SSEL1(1)
TXD[1:0](1)
RXD[1:0](1)
DSR1(1), CTS1(1),
RTS1(1), DTR1(1),
DCD1(1), RI1(1)
002aad175
(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) SSP interface and high-speed GPIO are available on LPC2114/01 and LPC2124/01 only.
Fig 1. Block diagram
LPC2114_2124_6
Product data sheet
Rev. 06 — 10 December 2007
© NXP B.V. 2007. All rights reserved.
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