LE80536 Datasheet PDF - Intel

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LE80536
Intel

Part Number LE80536
Description Processor on 90 nm
Page 30 Pages


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Intel® Pentium® M Processor on
90 nm Process with 2-MB L2
Cache
Datasheet
July 2005
Document Number: 302189-007



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IINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Pentium® M Processor on 90nm Process with 2 MB L2 Cache may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across
different processor families. See www.intel.com/products/processor_number for details.
Intel, Pentium, Celeron, MMX, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the
United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2004—2005, Intel Corporation. All rights reserved
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Content
1 Introduction.................................................................................................................................... 7
1.1 Terminology .......................................................................................................................... 9
1.2 References ........................................................................................................................... 9
2 Low Power Features.................................................................................................................... 11
2.1 Clock Control and Low Power States ................................................................................. 11
2.1.1 Normal State .......................................................................................................... 11
2.1.2 AutoHALT Power-Down State ............................................................................... 11
2.1.3 Stop-Grant State .................................................................................................... 12
2.1.4 HALT/Grant Snoop State ....................................................................................... 12
2.1.5 Sleep State ............................................................................................................ 13
2.1.6 Deep Sleep State................................................................................................... 13
2.1.7 Deeper Sleep State ............................................................................................... 14
2.2 Enhanced Intel SpeedStep® Technology ........................................................................... 14
2.3 Front Side Bus Low Power Enhancements ........................................................................ 15
2.4 Processor Power Status Indicator (PSI#) Signal ................................................................ 15
3 Electrical Specifications ............................................................................................................. 17
3.1 Power and Ground Pins...................................................................................................... 17
3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking ................................................... 17
3.2 Voltage Identification .......................................................................................................... 17
3.3 Catastrophic Thermal Protection ........................................................................................ 18
3.4 Signal Terminations and Unused Pins................................................................................ 19
3.5 FSB Frequency Select Signals (BSEL[1:0]) ....................................................................... 19
3.6 FSB Signal Groups ............................................................................................................. 19
3.7 CMOS Signals .................................................................................................................... 20
3.8 Maximum Ratings ............................................................................................................... 21
3.9 Processor DC Specifications ..............................................................................................21
4 Package Mechanical Specifications and Pin Information ....................................................... 49
4.1 Processor Pinout and Pin List............................................................................................. 56
4.2 Alphabetical Signals Reference .......................................................................................... 72
5 Thermal Specifications and Design Considerations................................................................ 79
5.1 Thermal Specifications ....................................................................................................... 82
5.1.1 Thermal Diode ....................................................................................................... 82
5.1.2 Thermal Diode Offset............................................................................................. 83
5.1.3 Intel® Thermal Monitor........................................................................................... 84
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Figures
2-1 Clock Control States................................................................................................................... 11
3-1 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#A)............................ 32
3-2 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#A) ................... 33
3-3 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#B)............................ 34
3-4 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#B) ................... 35
3-5 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#C) ........................... 36
3-6 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#C) ................... 37
3-7 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#D) ........................... 38
3-8 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#D) ................... 39
3-9 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#E)............................ 40
3-10 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#E) ................... 41
3-11 Active VCC and ICC Load Line .................................................................................................. 44
3-12 Deep Sleep VCC and ICC Load Line ......................................................................................... 45
4-1 Micro-FCPGA Package Top and Bottom Isometric Views ......................................................... 49
4-2 Micro-FCPGA Package - Top and Side Views ........................................................................... 50
4-3 Micro-FCPGA Package - Bottom View ....................................................................................... 51
4-4 Micro-FCBGA Package Top and Bottom Isometric Views ......................................................... 53
4-5 Micro-FCBGA Package Top and Side Views ............................................................................. 54
4-6 Micro-FCBGA Package Bottom View ......................................................................................... 56
4-7 The Coordinates of the Processor Pins as Viewed from the Top of the Package ...................... 57
4 Datasheet



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