KMM372V3200CK4 Datasheet PDF - Samsung Semiconductor

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KMM372V3200CK4
Samsung Semiconductor

Part Number KMM372V3200CK4
Description DRAM Module
Page 18 Pages


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DRAM MODULE
KMM372V320(8)0CK4
KMM372V320(8)0CK4 Fast Page Mode
32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V
GENERAL DESCRIPTION
The Samsung KMM372V320(8)0C is a 32Mx72bits Dynamic
RAM high density memory module. The Samsung
KMM372V320(8)0C consists of thirty-six CMOS 16Mx4bits
DRAMs in SOJ 400mil packages and two 16 bits driver IC in
TSSOP package mounted on a 168-pin glass-epoxy sub-
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on
the printed circuit board for each DRAM. The
KMM372V320(8)0C is a Dual In-line Memory Module and is
intended for mounting into 168 pin edge connector sockets.
PERFORMANCE RANGE
Speed
-5
tRAC
50ns
tCAC
18ns
tRC
90ns
tPC
35ns
-6
60ns
20ns
110ns
40ns
FEATURES
• Part Identification
Part number
PKG Ref. CBR Ref. ROR Ref.
KMM372V3200CK4 SOJ 4K
4K/64ms
KMM372V3280CK4 SOJ 8K 4K/64ms 8K/64ms
• Fast Page Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
• LVTTL compatible inputs and outputs
• Single 3.3V±0.3V power supply
• JEDEC standard pinout & Buffered PDpin
• Buffered input except RAS and DQ
• PCB : Height(2000mil), double sided component
PIN CONFIGURATIONS
PIN NAMES
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
Pin Names
Function
1 VSS 29 *CAS2 57 DQ22 85 VSS 113 *CAS3 141 DQ58
2 DQ0 30 RAS0 58 DQ23 86 DQ36 114 RAS1 142 DQ59
3 DQ1 31 OE0 59 VCC 87 DQ37 115 RFU 143 VCC
4 DQ2 32 VSS 60 DQ24 88 DQ38 116 VSS 144 DQ60
5 DQ3 33 A0 61 RFU 89 DQ39 117 A1 145 RFU
6 VCC 34 A2 62 RFU 90 VCC 118 A3 146 RFU
7 DQ4 35 A4 63 RFU 91 DQ40 119 A5 147 RFU
8 DQ5 36 A6 64 RFU 92 DQ41 120 A7 148 RFU
9 DQ6 37 A8 65 DQ25 93 DQ42 121 A9 149 DQ61
10 DQ7 38 A10 66 DQ26 94 DQ43 122 A11 150 DQ62
11 DQ8 39 A12 67 DQ27 95 DQ44 123 *A13 151 DQ63
12 VSS 40 VCC 68 VSS 96 VSS 124 VCC 152 VSS
13 DQ9 41 RFU 69 DQ28 97 DQ45 125 RFU 153 DQ64
14 DQ10 42 RFU 70 DQ29 98 DQ46 126 B0 154 DQ65
15 DQ11 43 VSS 71 DQ30 99 DQ47 127 VSS 155 DQ66
16 DQ12 44 OE2 72 DQ31 100 DQ48 128 RFU 156 DQ67
17 DQ13 45 RAS2 73 VCC 101 DQ49 129 RAS3 157 VCC
18 VCC 46 CAS4 74 DQ32 102 VCC 130 CAS5 158 DQ68
19 DQ14 47 *CAS6 75 DQ33 103 DQ50 131 *CAS7 159 DQ69
20 DQ15 48 W2 76 DQ34 104 DQ51 132 PDE 160 DQ70
21 DQ16 49 VCC 77 DQ35 105 DQ52 133 VCC 161 DQ71
22 DQ17 50 RSVD 78 VSS 106 DQ53 134 RSVD 162 VSS
23 VSS 51 RSVD 79 PD1 107 VSS 135 RSVD 163 PD2
24 RSVD 52 DQ18 80 PD3 108 RSVD 136 DQ54 164 PD4
25 RSVD 53 DQ19 81 PD5 109 RSVD 137 DQ55 165 PD6
26 VCC 54 VSS 82 PD7 110 VCC 138 VSS 166 PD8
27 W0 55 DQ20 83 ID0 111 RFU 139 DQ56 167 ID1
28 CAS0 56 DQ21 84 VCC 112 CAS1 140 DQ57 168 VCC
NOTE : A12 is used for only KMM372V3280CK4 (8K Ref.)
A0, B0, A1 - A11 Address Input(4K ref)
A0, B0, A1 - A12 Address Input(8K ref)
DQ0 - DQ71
Data In/Out
W0, W2
Read/Write Enable
OE0, OE2
Output Enable
RAS0 - RAS3
Row Address Strobe
CAS0, 1,4,5
Column Address Strobe
VCC Power(+3.3V)
VSS Ground
NC No Connection
PDE
Presence Detect Enable
PD1 - 8
Presence Detect
ID0 - 1
ID bit
RSVD
Reserved Use
RFU
Reserved for Future Use
Pins marked *are not used in this module.
PD & ID Table
Pin
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
50NS
1
0
0
0
0
0
0
0
60NS
1
0
0
0
0
1
1
0
PD Note :PD & ID Terminals must each be pulled up through a register to VCC at the next higher
ID0
ID1
0
0
level assembly. PDs will be either open (NC) or driven to VSS via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C
ID Note : IDs will be either open (NC) or connected directly to VSS without a buffer.
ID : 0 for Vss & 1 for N.C
0
0



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DRAM MODULE
KMM372V320(8)0CK4
FUNCTIONAL BLOCK DIAGRAM
RAS0
CAS0
OE0
W0
A0
A1-A11(A12)
RAS1
CAS1
DQ0-35
DQ0
U0 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U18
DQ0
U1 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U19
DQ0
U2 DQ1
DQ2
DQ3
DQ0
U3 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U20
DQ0
DQ1
DQ2
DQ3
U21
DQ0
DQ1
U4 DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U22
DQ0
U5 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U23
DQ0
U6 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U24
DQ0
U7 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U25
RAS2
CAS4
DQ36-71
DQ0
U9 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U27
DQ0
U10 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U28
DQ0
U11 DQ1
DQ2
DQ3
DQ0
U12 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U29
DQ0
DQ1
DQ2
DQ3
U30
DQ0
DQ1
U13 DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U31
DQ0
U14 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U32
DQ0
U15 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U33
DQ0
U16 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U34
RAS3
CAS5
OE2
W2
B0
A1-A11(A12)
DQ0
U8 DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U26
NOTE : A12 is used for only KMM372V3280CK4(8K Ref.)
Vcc
0.1 or 0.22uF Capacitor
under each DRAM
To all DRAMs
Vss
DQ0
U17 DQ1
DQ2
DQ3
A0
B0
A1-A11(A12)
W0, OE0
W2, OE2
DQ0
DQ1
DQ2
DQ3
U35
U0-U8, U18-U26
U9-U17, U27-U35
U0-U35
U0-U8, U18-U26
U9-U17, U27-U35



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DRAM MODULE
KMM372V320(8)0CK4
ABSOLUTE MAXIMUM RATINGS *
Item
Symbol
Rating
Unit
Voltage on any pin relative VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Output Current
VIN, VOUT
VCC
Tstg
PD
IOS
-0.5 to +4.6
-0.5 to +4.6
-55 to +125
36
50
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
*1 : VCC+1.3V at pulse width15ns, which is measured at VCC.
*2 : -1.3V at pulse width15ns, which is measured at VSS.
Min
3.0
0
2.0
-0.3*2
Typ
Max
Unit
3.3 3.6
00
- VCC+0.3*1
- 0.8
V
V
V
V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
Symbol
Speedl
KMM372V3200CK4
Min Max
KMM372V3280CK4
Min Max
ICC1
-5
-6
- 1998 - 1458
- 1818 - 1278
ICC2 Dont care
-
100
-
100
ICC3
-5
-6
-
-
1998
1818
-
-
1458
1278
ICC4
-5
-6
-
-
1098
918
-
-
1098
918
ICC5 Dont care
-
30
-
30
ICC6
-5
-6
-
-
1998
1818
-
-
1998
1818
II(L)
IO(L)
Dont care
-10
-10
10
10
-10
-10
10
10
VOH
VOL
Dont care
2.4
-
-
0.4
2.4
-
-
0.4
ICC1* : Operating Current * (RAS, CAS, Address cycling @tRC=min)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
ICC4* : Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min)
ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V)
ICC6* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
I(IL) : Input Leakage Current (Any input 0¡Â VIN¡Â Vcc+0.3V, all other pins not under test=0 V)
I(OL) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc)
VOH : Output High Voltage Level (IOH = -2mA)
VOL : Output Low Voltage Level (IOL = 2mA)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
* NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one Fast page mode cycle time, tPC.



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DRAM MODULE
KMM372V320(8)0CK4
CAPACITANCE (TA = 25°C, f = 1MHz)
Item
Symbol
Input capacitance[A0, B0, A1 - A12]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0 - RAS3]
Input capacitance[CAS0, CAS1,4,5]
Input/Output capacitance[DQ0 - 71]
CIN1
CIN2
CIN3
CIN4
CDQ
Min
-
-
-
-
-
Max
20
20
73
20
24
AC CHARACTERISTICS (0°CTA70°C, VCC=3.3V±0.3V. See notes 1,2.)
Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referencde to CAS
Read command hold referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data in set-up time
Data in hold time
Refresh period(4K & 8K)
Write command set-up time
CAS to W delay time
Column address to W delay time
CAS prechange to W delay time
Symbol
tRC
tRWC
tRAC
tCAC
tAA
tCLZ
tOFF
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
tDS
tDH
tREF
tWCS
tCWD
tAWD
tCPWD
-5
Min Max
90
133
50
18
30
5
5 18
1 50
30
50 10K
18
48
13 10K
18 32
13 20
10
5
8
0
10
30
0
0
-2
10
10
20
13
-2
15
64
0
36
48
53
-6
Min Max
110
155
60
20
35
5
5 20
1 50
40
60 10K
20
58
15 10K
18 40
13 25
10
5
8
0
10
35
0
0
-2
10
10
20
15
-2
15
64
0
40
55
60
Unit
pF
pF
pF
pF
pF
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
Note
3,4,10
3,4,5,11
3,10,11
3,11
6,11
2
11
11
4,11
10,11
11
11
11
11
8
8,11
11
9,11
9,11
7
7
7
7



KMM372V3200CK4 datasheet pdf
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KMM372V3200CK4 DRAM Module KMM372V3200CK4
Samsung Semiconductor
KMM372V3200CK4 pdf
KMM372V3200CK4 DRAM Module KMM372V3200CK4
Samsung Semiconductor
KMM372V3200CK4 pdf

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