KMM372F213CK Datasheet PDF - Samsung Semiconductor

www.Datasheet-PDF.com

KMM372F213CK
Samsung Semiconductor

Part Number KMM372F213CK
Description DRAM Module
Page 20 Pages


KMM372F213CK datasheet pdf
Download PDF
KMM372F213CK pdf
View PDF for Mobile

No Preview Available !

DRAM MODULE
KMM372F213CK/CS
KMM372F213CK/CS EDO Mode
2M x 72 DRAM DIMM with ECC using 2Mx8, 2K Refresh, 3.3V
GENERAL DESCRIPTION
The Samsung KMM372F213C is a 2Mx72bits Dynamic RAM
high density memory module. The Samsung KMM372F213C
consists of nine CMOS 2Mx8bits DRAMs in SOJ/TSOP-II
300mil package, and two 16bits driver IC in 48pin TSSOP
package mounted on a 168-pin glass-epoxy substrate. A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit
board for each DRAM. The KMM372F213C is a Dual In-line
Memory Module and is intended for mounting into 168-pin
edge connector sockets.
PERFORMANCE RANGE
Speed
-5
tRAC
50ns
tCAC
18ns
tRC
84ns
tHPC
20ns
-6
60ns
20ns
104ns
25ns
FEATURES
• Part Identification
- KMM372F213CK (2048 cycles/32ms Ref., SOJ)
- KMM372F213CS (2048 cycles/32ms Ref., TSOP)
• Fast Page Mode with Extended Data Out Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
• LVTTL compatible inputs and outputs
• Single 3.3V±0.3V power supply
• JEDEC standard pinout & Buffered PDpin
• Buffered input except RAS and DQ
• PCB : Height(1000mil), Single sided component
PIN CONFIGURATIONS
PIN NAMES
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
Pin Names
Function
1 VSS 29 RSVD 57 DQ22 85 VSS 113 RSVD 141 DQ58
2 DQ0 30 RAS0 58 DQ23 86 DQ36 114 *RAS1 142 DQ59
3 DQ1 31 OE0 59 VCC 87 DQ37 115 RFU 143 VCC
4 DQ2 32 VSS 60 DQ24 88 DQ38 116 VSS 144 DQ60
5 DQ3 33 A0 61 RFU 89 DQ39 117 A1 145 RFU
6 VCC 34 A2 62 RFU 90 VCC 118 A3 146 RFU
7 DQ4 35 A4 63 RFU 91 DQ40 119 A5 147 RFU
8 DQ5 36 A6 64 RFU 92 DQ41 120 A7 148 RFU
9 DQ6 37 A8 65 DQ25 93 DQ42 121 A9 149 DQ61
10 DQ7 38 A10 66 DQ26 94 DQ43 122 *A11 150 DQ62
11 DQ8 39 *A12 67 DQ27 95 DQ44 123 *A13 151 DQ63
12 VSS 40 VCC 68 VSS 96 VSS 124 VCC 152 VSS
13 DQ9 41 RFU 69 DQ28 97 DQ45 125 RFU 153 DQ64
14 DQ10 42 RFU 70 DQ29 98 DQ46 126 B0 154 DQ65
15 DQ11 43 VSS 71 DQ30 99 DQ47 127 VSS 155 DQ66
16 DQ12 44 OE2 72 DQ31 100 DQ48 128 RFU 156 DQ67
17 DQ13 45 RAS2 73 VCC 101 DQ49 129 *RAS3 157 VCC
18 VCC 46 CAS4 74 DQ32 102 VCC 130 *CAS5 158 DQ68
19 DQ14 47 RSVD 75 DQ33 103 DQ50 131 RSVD 159 DQ69
20 DQ15 48 W2 76 DQ34 104 DQ51 132 PDE 160 DQ70
21 DQ16 49 VCC 77 DQ35 105 DQ52 133 VCC 161 DQ71
22 DQ17 50 RSVD 78 VSS 106 DQ53 134 RSVD 162 VSS
23 VSS 51 RSVD 79 PD1 107 VSS 135 RSVD 163 PD2
24 RSVD 52 DQ18 80 PD3 108 RSVD 136 DQ54 164 PD4
25 RSVD 53 DQ19 81 PD5 109 RSVD 137 DQ55 165 PD6
26 VCC 54 VSS 82 PD7 110 VCC 138 VSS 166 PD8
27 W0 55 DQ20 83 ID0 111 RFU 139 DQ56 167 ID1
28 CAS0 56 DQ21 84 VCC 112 *CAS1 140 DQ57 168 VCC
A0, B0, A1 - A10 Address Input
DQ0 - DQ71
Data In/Out
W0, W2
Read/Write Enable
OE, OE2
Output Enable
RAS0, RAS2
Row Address Strobe
CAS0, CAS4
Column Address Strobe
VCC Power(+3.3V)
VSS Ground
NC No Connection
PDE
Presence Detect Enable
PD1 - 8
Presence Detect
ID0 - 1
ID bit
RSVD
Reserved Use
RFU
Reserved for Future Use
Pins marked *are not used in this module.
PD & ID Table
Pin
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
50NS
1
0
0
1
1
0
0
0
60NS
1
0
0
1
1
1
1
0
PD Note : PD & ID Terminals must each be pulled up through a resister to V CC at the next higher
ID0
ID1
0
0
level assembly. PDs will be either open (NC) or driven to V SS via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C
ID Note : IDs will be either open (NC) or connected directly to V SS without a buffer.
ID : 0 for Vss & 1 for N.C
0
0



No Preview Available !

DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
RAS0
CAS0
W0
OE0
A0
A1-A10
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
U0
RAS2
CAS4
W2
OE2
B0
A1-A10
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
U1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
U2
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
U3
DQ64
DQ65
DQ66
DQ67
DQ68
DQ69
DQ70
DQ71
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
U4
Vcc
0.1 or 0.22uF Capacitor
under each DRAM
To all DRAMs
Vss
A0
B0
A1-An
W0, 2
OE0, 2
KMM372F213CK/CS
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
U5
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
U6
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
U7
DQ0
DQ1
DQ2
DQ3
DQ4
DD5
DQ6
DQ7
U8
U0-U4
U5-U8
A1-An : U0-U8



No Preview Available !

DRAM MODULE
KMM372F213CK/CS
ABSOLUTE MAXIMUM RATINGS *
Item
Symbol
Rating
Unit
Voltage on any pin relative VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Output Current
VIN, VOUT
VCC
Tstg
PD
IOS
-0.5 to +4.6
-0.5 to +4.6
-55 to +125
9
50
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
Typ
Max
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
3.0
0
2.0
-0.3*2
3.3 3.6
00
- VCC+0.3*1
- 0.8
*1 : VCC+1.3V/15ns, Pulse width is measured at VCC.
*2 : -1.3V/15ns, Pulse width is measured at VSS.
Unit
V
V
V
V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
Symbol
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
II(L)
IO(L)
VOH
VOL
Speed
-5
-6
Dont care
-5
-6
-5
-6
Dont care
-5
-6
Dont care
Dont care
KMM372F213CK/CS
Min Max
- 990
- 900
- 100
- 990
- 900
- 810
- 720
- 30
- 990
- 900
-25 25
-5 5
2.4 -
- 0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
ICC1* : Operating Current * (RAS, CAS, Address cycling @tRC=min)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
ICC4* : EDO Mode Current * (RAS=VIL, CAS cycling : tHPC=min)
ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V)
ICC6* : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
II(L) : Input Leakage Current (Any input 0VINVcc+0.3V, all other pins not under test=0 V)
IO(L) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc)
VOH : Output High Voltage Level (IOH = -2mA)
VOL : Output Low Voltage Level (IOL = 2mA)
* NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one hyper page mode cycle, tHPC.



No Preview Available !

DRAM MODULE
KMM372F213CK/CS
CAPACITANCE (TA = 25°C, Vcc=3.3V, f = 1MHz)
Item
Symbol
Input capacitance[A0-A10, B0]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0, RAS2]
Input capacitance[CAS0, CAS4]
Input/Output capacitance[DQ0 - 71]
CIN1
CIN2
CIN3
CIN4
CDQ1
Min
-
-
-
-
-
Max
20
20
45
20
20
AC CHARACTERISTICS (0°CTA70°C, VCC=3.3V±0.3V. See notes 1,2.)
Test condition : Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF
Parameter
Symbol
-5
Min Max
-6
Min Max
Random read or write cycle time
tRC 84
104
Read-modify-write cycle time
tRWC
131
155
Access time from RAS
tRAC
50 60
Access time from CAS
tCAC
18 20
Access time from column address
tAA
30 35
CAS to output in Low-Z
tCLZ
8
8
OE to output in Low-Z
tOLZ
8
8
Output buffer turn-off delay from CAS
tCEZ
8 18 8 20
Transition time(rise and fall)
tT 2 50 2 50
RAS precharge time
tRP 30
40
RAS pulse width
tRAS
50 10K 60 10K
RAS hold time
tRSH
18
20
CAS hold time
tCSH
36
43
CAS pulse width
tCAS
8 10K 10 10K
RAS to CAS delay time
tRCD
18 32 18 40
RAS to column address delay time
tRAD
13 20 13 25
CAS to RAS precharge time
tCRP
10
10
Row address set-up time
tASR
5
5
Row address hold time
tRAH
8
8
Column address set-up time
tASC
0
0
Column address hold time
tCAH
8
10
Column address to RAS lead time
tRAL
30
35
Read command set-up time
tRCS
0
0
Read command hold time referenced to CAS tRCH
0
0
Read command hold time referenced to RAS tRRH
-2
-2
Write command hold time
tWCH
10
10
Write command pulse width
tWP 10
10
Write command to RAS lead time
tRWL
18
20
Write command to CAS lead time
tCWL
8
10
Data set-up time
tDS -2
-2
Data hold time
tDH 13
15
Refresh period(2K Ref.)
tREF
32 32
Write command set-up time
tWCS
0
0
CAS to W delay time
tCWD
36
40
RAS to W delay time
tRWD
71
83
Unit
pF
pF
pF
pF
pF
Unit
Note
ns
ns
ns 3,4,10
ns 3,4,5,14
ns 3,10,14
ns 3,14
ns 3,14
ns 6,11,12,14
ns 2
ns
ns
ns 14
ns 14
ns 13
ns 4,14
ns 10,14
ns 14
ns 14
ns 14
ns
ns
ns 14
ns
ns 8
ns 8,14
ns
ns
ns 14
ns
ns 9,14
ns 9,14
ms
ns 7
ns 7
ns 7,14



KMM372F213CK datasheet pdf
Download PDF
KMM372F213CK pdf
View PDF for Mobile


Related : Start with KMM372F213C Part Numbers by
KMM372F213CK DRAM Module KMM372F213CK
Samsung Semiconductor
KMM372F213CK pdf
KMM372F213CS DRAM Module KMM372F213CS
Samsung Semiconductor
KMM372F213CS pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact