K3P7V1000B-YC Datasheet PDF - Samsung semiconductor

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K3P7V1000B-YC
Samsung semiconductor

Part Number K3P7V1000B-YC
Description 64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM
Page 4 Pages


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K3P7V(U)1000B-YC
CMOS MASK ROM
64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM
FEATURES
Switchable organization
8,388,608 x 8(byte mode)
4,194,304 x 16(word mode)
Fast access time
Random Access Time/Page Access Time
3.3V Operation : 100/30ns(Max.)@CL=50pF,
120/40ns(Max.)@CL=100pF
3.0V Operation : 120/40ns(Max.)@CL=100pF
8 Words / 16 Bytes page access
Supply voltage : single +3.0V/ single +3.3V
Current consumption
Operating : 60mA(Max.)
Standby : 50µA(Max.)
Fully static operation
All inputs and outputs TTL compatible
Three state outputs
Package
K3P7V(U)1000B-YC : 48-TSOP1-1218
GENERAL DESCRIPTION
The K3P7V(U)1000B-YC is a fully static mask programmable
ROM fabricated using silicon gate CMOS process technology,
and is organized either as 8,388,608 x 8 bit(byte mode) or as
4,194,304 x 16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device includes page read mode function, page read mode
allows 8 words (or 16 bytes) of data to read fast in the same
page, CE and A3 ~ A21 should not be changed.
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3P7V(U)1000B-YC is packaged in a 48-TSOP1.
FUNCTIONAL BLOCK DIAGRAM
A21
.
.
.
.
.
.
.
.
A3
A0~A2
A-1
X
BUFFERS
AND
DECODER
Y
BUFFERS
AND
DECODER
CE
OE
BHE
CONTROL
LOGIC
MEMORY CELL
MATRIX
(4,194,304x16/
8,388,608x8)
SENSE AMP.
DATA OUT
BUFFERS
...
Q0/Q8 Q7/Q15
Pin Name
A0 - A2
A3 - A21
Q0 - Q14
Q15 /A-1
BHE
CE
OE
VCC
Vss
N.C
Pin Function
Page Address Inputs
Address Inputs
Data Outputs
Output 15(Word mode)/
LSB Address(Byte mode)
Word/Byte selection
Chip Enable
Output Enable
Power
Ground
No Connection
Free Datasheet http://www.datasheet4u.com/



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K3P7V(U)1000B-YC
PIN CONFIGURATION
CMOS MASK ROM
BHE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
A21
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TSOP1
48 VSS
47 VSS
46 Q15/A-1
45 Q7
44 Q14
43 Q6
42 Q13
41 Q5
40 Q12
39 Q4
38 VCC
37 VCC
36 N.C
35 Q11
34 Q3
33 Q10
32 Q2
31 Q9
30 Q1
29 Q8
28 Q0
27 OE
26 VSS
25 VSS
K3P7V(U)1000B-YC
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Unit
Voltage on Any Pin Relative to VSS
Temperature Under Bias
Storage Temperature
VIN
TBIAS
TSTG
-0.3 to +4.5
-10 to +85
-55 to +150
V
°C
°C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item
Symbol
Min
Typ
Max
Supply Voltage
VCC
2.7/3.0
3.0/3.3
3.3/3.6
Supply Voltage
VSS 0 0 0
Unit
V
V
DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min Max Unit
Operating Current
ICC
Cycle=5MHZ, all outputs open, CE=OE=VIL, VCC=3.3V±0.3V
VIN=0.45V to 2.4V (AC Test Condition)
VCC=3.0V±0.3V
-
60 mA
50 mA
Standby Current(TTL)
ISB1 CE=VIH, all outputs open
500 µA
Standby Current(CMOS)
ISB2 CE=VCC, all outputs open
50 µA
Input Leakage Current
ILI VIN=0 to VCC
- 10 µA
Output Leakage Current
ILO VOUT=0 to VCC
- 10 µA
Input High Voltage, All Inputs VIH
2.0 VCC+0.3 V
Input Low Voltage, All Inputs VIL
-0.3 0.6 V
Output High Voltage Level
VOH IOH=-400µA
2.4 - V
Output Low Voltage Level
VOL IOL=2.1mA
- 0.4 V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
Free Datasheet http://www.datasheet4u.com/



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K3P7V(U)1000B-YC
MODE SELECTION
CE OE
HX
LH
LL
BHE
X
X
H
L
CMOS MASK ROM
Q15/A-1
X
X
Output
Input
Mode
Standby
Operating
Operating
Operating
Data
High-Z
High-Z
Q0~Q15 : Dout
Q0~Q7 : Dout
Q8~Q14 : Hi-Z
Power
Standby
Active
Active
Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item
Symbol
Output Capacitance
Input Capacitance
COUT
CIN
NOTE : Capacitance is periodically sampled and not 100% tested.
Test Conditions
VOUT=0V
VIN=0V
Min
-
-
Max
12
12
Unit
pF
pF
AC CHARACTERISTICS(TA=0°C to +70°C,VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
TEST CONDITIONS
Item
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Levels
Output Loads
Value
0.45V to 2.4V
10ns
1.5V
1 TTL Gate and CL=50pF or 100pF
READ CYCLE
Item
Symbol
Read Cycle Time
Chip Enable Access Time
Address Access Time
Page Address Access Time
Output Enable Access Time
Output or Chip Disable to
Output High-Z
Output Hold from Address Change
tRC
tACE
tAA
tPA
tOE
tDF
tOH
NOTE : Page Address is determined as below.
Word mode (BHE=VIH) : A0, A1, A2
Byte mode (BHE=VIL) : A-1, A0, A1, A2
K3P7V1000B-YC10
(CL=50pF)
Min Max
100
100
100
30
30
20
0
K3P7V1000B-YC12
(CL=100pF)
Min Max
120
120
120
40
40
20
0
K3P7U1000B-YC12
(CL=100pF)
Min Max
120
120
120
40
40
Unit
ns
ns
ns
ns
ns
20 ns
0 ns
Free Datasheet http://www.datasheet4u.com/



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K3P7V(U)1000B-YC
TIMING DIAGRAM
READ
ADD
A0~A21
A-1(*1)
CE
OE
ADD1
tACE
tRC
tOE
DOUT
D0~D7
D8~D15(*2)
PAGE READ
VALID DATA
CMOS MASK ROM
ADD2
tAA
tOH
VALID DATA
tDF(*3)
CE
tDF(*3)
OE
ADD
A3~A21
ADD
A0,A1,A2
A -1(*1)
DOUT
D0~D7
D8~D15(*2)
1 st
tAA
2 nd
tPA
3 rd
VALID DATA
VALID DATA
VALID DATA
VALID DATA
NOTES :
*1.Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)
*2. Word Mode only.(BHE = VIH)
*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.
Free Datasheet http://www.datasheet4u.com/



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K3P7V1000B-YC 64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM K3P7V1000B-YC
Samsung semiconductor
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