ISL8701A Datasheet PDF - Intersil Corporation

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ISL8701A
Intersil Corporation

Part Number ISL8701A
Description (ISL8700A - ISL8705A) Adjustable Quad Sequencer
Page 12 Pages


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®
Data Sheet
ISL8700A, ISL8701A, ISL8702A,
ISL8703A, ISL8704A, ISL8705A
October 12, 2006
FN6381.0
Adjustable Quad Sequencer
The ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A,
ISL8705A family of ICs provide four delay adjustable
sequenced outputs while monitoring an input voltage all with
a minimum of external components.
High performance DSP, FPGA, µP and various sub-systems
require input power sequencing for proper functionality at
initial power up and the ISL870XA provides this function
while monitoring the distributed voltage for over and
undervoltage compliance.
These ICs operate over the +3.3V to +24V nominal voltage
range. All have a user adjustable time from UV and OV
voltage compliance to sequencing start via an external
capacitor when in auto start mode and adjustable time delay
to subsequent ENABLE output signal via external resistors.
Additionally, the ISL8702A, ISL8703A, ISL8704A and
ISL8705A provide I/O for sequencing on and off operation
(SEQ_EN) and for voltage window compliance reporting
(FAULT) over the +3.3V to +24V nominal voltage range.
Easily daisy chained for more than 4 sequenced signals.
Altogether, the ISL870XA provides these adjustable features
with a minimum of external BOM. See Figure 1 for typical
implementation.
Ordering Information
PART NUMBER PART
TEMP. PACKAGE PKG.
(Note 1)
MARKING RANGE (°C) (Pb-free) DWG. #
ISL8700AIBZ* ISL8700AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8701AIBZ* ISL8701AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8702AIBZ* ISL8702AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8703AIBZ* ISL8703AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8704AIBZ* ISL8704AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8705AIBZ* ISL8705AIBZ -40 to +85 14 Ld SOIC M14.15
ISL870XAEVAL1 Evaluation Platform
*Add “-T” suffix for tape and reel.
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Adjustable Delay to Subsequent Enable Signal
• Adjustable Delay to Sequence Auto Start
• Adjustable Distributed Voltage Monitoring
• Under and Overvoltage Adjustable Delay to Auto Start
Sequence
• I/O Options
ENABLE (ISL8700A, ISL8702A, ISL8704A) and
ENABLE# (ISL8701A, ISL8703A, ISL8705A)
SEQ_EN (ISL8702A, ISL8703A) and
SEQ_EN# (ISL8704A, ISL8705A)
• Voltage Compliance Fault Output
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Power Supply Sequencing
• System Timing Function
Pinout
ISL870XA
(14 LD SOIC)
TOP VIEW
ENABLE_D 1
ENABLE_C 2
ENABLE_B 3
ENABLE_A 4
OV 5
UV 6
GND 7
14 VIN
13 TD
12 TC
11 TB
10 TIME
9 SEQ_EN (NC on ISL8700A/01A)
8 FAULT (NC on ISL8700A/01A)
ISL8701A, ISL8703A, ISL8705A PINS 1-4 ARE ENABLE# FUNCTION
ISL8704A, ISL8705A PIN 9 IS SEQ_EN# FUNCTION
3.3-24V
Ru VIN ENABLE_A
SEQ_EN *
ENABLE_B
ENABLE_C
UV ENABLE_D
Rm
OV
FAULT *
GND TB TC TD TIME
Rl
EN
DC/DC
Vo1
EN
DC/DC
Vo2
EN
DC/DC
Vo3
EN
DC/DC
V04
* SEQ_EN and FAULT are not available on ISL8700A and ISL8701A
FIGURE 1. ISL870XA IMPLEMENTATION
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.



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ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
Absolute Maximum Ratings
VIN, ENABLE(#), FAULT . . . . . . . . . . . . . . . . . . . . . . . 27V, to -0.3V
TIME, TB, TC, TD, UV, OV . . . . . . . . . . . . . . . . . . . . . +6V, to -0.3V
SEQ_EN(#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN+0.3V, to -0.3V
ENABLE, ENABLE # Output Current . . . . . . . . . . . . . . . . . . . 10mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (Nominal). . . . . . . . . . . . . . . . . . 3.3V to 24V
Thermal Information
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
14 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Nominal VIN = 3.3V to +24V, TA = TJ = -40°C to+85°C, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
UV AND OV INPUTS
UV/OV Rising Threshold
UV/OV Falling Threshold
UV/OV Hysteresis
UV/OV Input Current
TIME, ENABLE/ENABLE# OUTPUTS
VUVRvth
VUVFvth
VUVhys
IUV
VUVRvth - VUVFvth
1.16 1.21
1.06 1.10
- 104
- 10
TIME Pin Charging Current
TIME Pin Threshold
Time from VIN Valid to ENABLE_A
Time from VIN Invalid to Shutdown
ENABLE Output Resistance
ITIME
VTIME_VTH
tVINSEQpd
tVINSEQpd_10
tVINSEQpd500
tshutdown
REN
SEQ_EN = high, CTIME = open
SEQ_EN = high, CTIME = 10nF
SEQ_EN = high, CTIME = 500nF
UV or OV to simultaneous shutdown
IENABLE = 1mA
- 2.6
1.9 2.0
- 30
- 7.7
- 435
--
- 100
ENABLE Output Low
ENABLE Pull-down Current
Delay to Subsequent ENABLE Turn-on/off
SEQUENCE ENABLE AND FAULT I/O
Vol
Ipulld
tdel_120
tdel_3
tdel_0
IENABLE = 1mA
ENABLE = 1V
RTX = 120kΩ
RTX = 3kΩ
RTX = 0Ω
- 0.1
10 15
155 195
3.5 4.7
- 0.5
VIN Valid to FAULT Low
VIN Invalid to FAULT High
FAULT Pull-down Current
tFLTL
tFLTH
FAULT = 1V
15 30
- 0.5
10 15
SEQ_EN Pull-up Voltage
SEQ_EN Low Threshold Voltage
SEQ_EN High Threshold Voltage
Delay to ENABLE_A Deasserted
BIAS
VSEQ
SEQ_EN open
VilSEQ_EN
VihSEQ_EN
tSEQ_EN_ENA SEQ_EN low to ENABLE_A low
- 2.4
--
1.2 -
- 0.2
IC Supply Current
VIN Power On Reset
IVIN_3.3V
IVIN_12V
IVIN_24V
VIN_POR
VIN = 3.3V
VIN = 12V
VIN = 24V
VIN low to high
- 191
- 246
- 286
- 2.3
MAX
1.28
1.18
-
-
-
2.25
-
-
-
1
-
-
-
240
6
-
50
-
-
-
0.3
-
1
-
400
-
2.8
UNIT
V
V
mV
nA
μA
V
μs
ms
ms
μs
Ω
V
mA
ms
ms
ms
μs
μs
mA
V
V
V
μs
μA
μA
μA
V
2 FN6381.0
October 12, 2006



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ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
Pin Descriptions
PINS
8700A 8701A 8702A 8703A 8704A 8705A PIN NAME
FUNCTION DESCRIPTION
NA 1 NA 1 NA 1 ENABLE#_D Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output
to sequence off for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias.
1 NA 1 NA 1 NA ENABLE_D Active high open drain sequenced output. Sequenced on after ENABLE_C and first output
to sequence off for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V.
NA 2 NA 2 NA 2 ENABLE#_C Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced
off after ENABLE#_D for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias.
2 NA 2 NA 2 NA ENABLE_C Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced
off after ENABLE_D for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V.
NA 3 NA 3 NA 3 ENABLE#_B Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced
off after ENABLE#_C for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias.
3 NA 3 NA 3 NA ENABLE_B Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced
off after ENABLE_C for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V.
NA 4 NA 4 NA 4 ENABLE#_A Active low open drain sequenced output. Sequenced on after CTIME period and sequenced
off after ENABLE#_B for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias.
4 NA 4 NA 4 NA ENABLE_A Active high open drain sequenced output. Sequenced on after CTIME period and
sequenced off after ENABLE_B for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN
< 1V.
555555
OV The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull-ups.
666666
UV The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull-ups.
777777
GND IC ground.
NA NA
NA NA
8
9
8 8 8 FAULT The VIN voltage when not within the desired UV to OV window will cause FAULT to be
released to be pulled high to a voltage equal to or less than VIN via an external resistor.
9 NA NA SEQ_EN This pin provides a sequence on signal input with a high input. Internally pulled high to ~2.4V.
NA NA NA NA 9
9 SEQ_EN# This pin provides a sequence on signal input with a low input. Internally pulled high to ~2.4V.
10 10 10 10 10 10
TIME
This pin provides a 2.6µA current output so that an adjustable VIN valid to sequencing on
and off start delay period is created with a capacitor to ground.
11 11 11 11 11 11
TB A resistor connected from this pin to ground determines the time delay from ENABLE_A
being active to ENABLE _B being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
12 12 12 12 12 12
TC A resistor connected from this pin to ground determines the time delay from ENABLE_B
being active to ENABLE _C being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
13 13 13 13 13 13
TD A resistor connected from this pin to ground determines the time delay from ENABLE_C
being active to ENABLE _D being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
14 14 14 14 14 14
VIN IC Bias Pin Nominally 3.3V to 24V
This pin requires a 1μF decoupling capacitor close to IC pin.
3 FN6381.0
October 12, 2006



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ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
Functional Block Diagram
VIN (2.8V MIN - 27V MAX)
SEQ_EN
UV
OV
FAULT
GND
TIME
VIN
VREF
VOLTAGE
1.17V
REFERENCE
+
- eo
+
-
30μs
VTIME_VTH
LOGIC
VIN
2.6μA
VIN INTERNAL VOLTAGE
3.5V
REGULATOR
2.0V VIN POR
PROGRAMMABLE
DELAY TIMER
ENABLE_A
ENABLE_B
ENABLE_C
ENABLE_D
Functional Description
The ISL870XA family of ICs provides four delay adjustable
sequenced outputs while monitoring a single distributed voltage
in the nominal range of 3.3V to 24V for both under and
overvoltage. Only when the voltage is in compliance will the
ISL870XA initiate the pre-programmed A-B-C-D sequence of
the ENABLE (ISL8700A, ISL8702A, ISL8704A) or ENABLE#
(ISL8701A, ISL8703A, ISL8705A) outputs. Although this IC has
a bias range of 3.3V to 24V it can monitor any voltage >1.22V
via the external divider if a suitable bias voltage is otherwise
provided.
During initial bias voltage (VIN) application the ISL8700A,
ISL8702A, ISL8704A ENABLE outputs are held low once
VIN = 1V whereas the ISL8701A, ISL8703A, ISL8705A
ENABLE# outputs follow the rising VIN. Once VIN > the V bias
power on reset threshold (POR) of 2.8V, VIN is constantly
monitored for compliance via the input voltage resistor divider
and the voltages on the UV and OV pins and reported by the
FAULT output. Internally, voltage regulators generate 3.5V and
1.17V ±5% voltage rails for internal usage once VIN > POR.
Once UV > 1.22V and with the SEQ_EN pin high or open,
(SEQ_EN# must be pulled low on ISL8704A, ISL8705A) the
auto sequence of the four ENABLE (ENABLE#) outputs begins
as the TIME pin charges its external capacitor with a 2.6µA
current source. The voltage on TIME is compared to the
internal reference (VTIME_VTH) comparator input and when
4
TB TC TD
greater than VTIME_VTH the ISL8700A, ISL8702A, ISL8704A
ENABLE_A is released to go high via an external pull-up
resistor or a pull-up in a DC/DC convertor enable input, for
example. Conversely, ENABLE#_A output will be pulled low at
this time on an ISL8701A, ISL8703A, ISL8705A. The time
delay generated by the external capacitor is to assure
continued voltage compliance within the programmed limits, as
during this time any OV or UV condition will halt the start-up
process. TIME cap is discharged once VTIME_VTH is met.
Once ENABLE_A is active (either released high on the
ISL8700A, ISL8702A, ISL8704A or pulled low, ISL8701A,
ISL8703A, ISL8705A) a counter is started and using the
resistor on TB as a timing component a delay is generated
before ENABLE_B is activated. At this time, the counter is
restarted using the resistor on TC as its timing component for
a separate timed delay until ENABLE_C is activated. This
process is repeated for the resistor on TD to complete the
A-B-C-D sequencing order of the ENABLE or ENABLE#
outputs. At any time during sequencing if an OV or UV event
is registered, all four ENABLE outputs will immediately return
to their reset state; low for ISL8700A, ISL8702A, ISL8704A
and high for ISL8701A, ISL8703A, ISL8705A. CTIME is
immediately discharged after initial ramp up thus waiting for
subsequent voltage compliance to restart. Once sequencing
is complete, any subsequently registered UV or OV event will
trigger an immediate and simultaneous reset of all ENABLE or
ENABLE# outputs.
FN6381.0
October 12, 2006



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