ISL8700A, ISL8701A, ISL8702A,
ISL8703A, ISL8704A, ISL8705A
October 12, 2006
Adjustable Quad Sequencer
The ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A,
ISL8705A family of ICs provide four delay adjustable
sequenced outputs while monitoring an input voltage all with
a minimum of external components.
High performance DSP, FPGA, µP and various sub-systems
require input power sequencing for proper functionality at
initial power up and the ISL870XA provides this function
while monitoring the distributed voltage for over and
These ICs operate over the +3.3V to +24V nominal voltage
range. All have a user adjustable time from UV and OV
voltage compliance to sequencing start via an external
capacitor when in auto start mode and adjustable time delay
to subsequent ENABLE output signal via external resistors.
Additionally, the ISL8702A, ISL8703A, ISL8704A and
ISL8705A provide I/O for sequencing on and off operation
(SEQ_EN) and for voltage window compliance reporting
(FAULT) over the +3.3V to +24V nominal voltage range.
Easily daisy chained for more than 4 sequenced signals.
Altogether, the ISL870XA provides these adjustable features
with a minimum of external BOM. See Figure 1 for typical
PART NUMBER PART
TEMP. PACKAGE PKG.
MARKING RANGE (°C) (Pb-free) DWG. #
ISL8700AIBZ* ISL8700AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8701AIBZ* ISL8701AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8702AIBZ* ISL8702AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8703AIBZ* ISL8703AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8704AIBZ* ISL8704AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8705AIBZ* ISL8705AIBZ -40 to +85 14 Ld SOIC M14.15
ISL870XAEVAL1 Evaluation Platform
*Add “-T” suffix for tape and reel.
1. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
• Adjustable Delay to Subsequent Enable Signal
• Adjustable Delay to Sequence Auto Start
• Adjustable Distributed Voltage Monitoring
• Under and Overvoltage Adjustable Delay to Auto Start
• I/O Options
ENABLE (ISL8700A, ISL8702A, ISL8704A) and
ENABLE# (ISL8701A, ISL8703A, ISL8705A)
SEQ_EN (ISL8702A, ISL8703A) and
SEQ_EN# (ISL8704A, ISL8705A)
• Voltage Compliance Fault Output
• Pb-Free Plus Anneal Available (RoHS Compliant)
• Power Supply Sequencing
• System Timing Function
(14 LD SOIC)
9 SEQ_EN (NC on ISL8700A/01A)
8 FAULT (NC on ISL8700A/01A)
ISL8701A, ISL8703A, ISL8705A PINS 1-4 ARE ENABLE# FUNCTION
ISL8704A, ISL8705A PIN 9 IS SEQ_EN# FUNCTION
Ru VIN ENABLE_A
GND TB TC TD TIME
* SEQ_EN and FAULT are not available on ISL8700A and ISL8701A
FIGURE 1. ISL870XA IMPLEMENTATION
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.