IS61NSCS51236 Datasheet PDF - Integrated Silicon Solution

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IS61NSCS51236
Integrated Silicon Solution

Part Number IS61NSCS51236
Description (IS61NSCS25672 / IS61NSCS51236) Synchronous SRAM
Page 30 Pages


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IS61NSCS25672
IS61NSCS51236
ΣRAM 256K x 72, 512K x 36
18Mb Synchronous SRAM
ISSI®
ADVANCE INFORMATION
JUNE 2001
Features
• JEDEC SigmaRam pinout and package standard
• Single 1.8V power supply (VCC): 1.7V (min)
to 1.9V (max)
• Dedicated output supply voltage (VCCQ): 1.8V
or 1.5V typical
• LVCMOS-compatible I/O interface
• Common data I/O pins (DQs)
• Single Data Rate (SDR) data transfers
• Pipelined (PL) read operations
• Double Late Write (DLW) write operations
• Burst and non-burst read and write operations,
selectable via dedicated control pin (ADV)
• Internally controlled Linear Burst address
sequencing during burst operations
• Burst length of 2, 3, or 4, with automatic address
wrap
• Full read/write coherency
• Byte write capability
• Two cycle deselect
• Single-ended input clock (CLK)
• Data-referenced output clocks (CQ/CQ)
• Selectable output driver impedance via dedicated
control pin (ZQ)
• Echo clock outputs track data output drivers
• Depth expansion capability (2 or 4 banks) via
programmable chip enables (E2, E3, EP2, EP3)
• JTAG boundary scan (subset of IEEE standard
1149.1)
• 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball
Grid Array (BGA) package
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
SigmaRAM Family Overview
The IS61NSCS series ΣRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
The implementations are 18,874,368-bit (18Mb) SRAMs.
These are the first in a family of wide, very low voltage CMOS
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking
systems.
ISSIs ΣRAMs are offered in a number of configurations that
emulate other synchronous SRAMs, such as Burst RAMs,
NBT RAMs, Late Write, or Double Data Rate (DDR) SRAMs.
The logical differences between the protocols employed by
these RAMs hinge mainly on various combinations of
address bursting, output data registering and write cueing.
ΣRAMs allow a user to implement the interface protocol best
suited to the task at hand.
This specific product is Common I/O, SDR, Double Late
Write & Pipelined Read (same as Pipelined NBT) and in
the family is identified as 1x1Dp.
This document contains ADVANCE INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best
possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01
1
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IS61NSCS25672
IS61NSCS51236
ISSI ®
Functional Description
Because SigmaRAM is a synchronous device, address,
data Inputs, and read/write control inputs are captured on
the rising edge of the input clock. Write cycles are
internally self-timed and initiated by the rising edge of the
clock input. This feature eliminates complex off-chip write
pulse generation required by asynchronous SRAMs and
simplifies input signal timing.
Single data rate ΣRAMs incorporate a rising-edge-triggered
output register. For read cycles, ΣRAM’s output data is
temporarily stored by the edge-triggered output register
during the access cycle and then released to the output
drivers at the next rising edge of clock.
IS61NSCS series ΣRAMs are implemented with ISSI’s
high performance CMOS technology and are packaged in
a 209-bump BGA.
IS61NSCS25672 PINOUT
256K x 72 Common I/OTop View
1234
A DQg
DQg
A
E2
B DQg
DQg
Bc
Bg
5
A
(16M)
NC
6
ADV
W
C DQg
DQg
Bh
D DQg
E DQPg
F DQc
G DQc
H DQc
J DQc
K CQ2
L DQh
M DQh
N DQh
P DQh
R DQPd
T DQd
U DQd
DQg
DQPc
DQc
DQc
DQc
DQc
CQ2
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
GND
VCCQ
GND
VCCQ
GND
VCCQ
CLK
VCCQ
GND
VCCQ
GND
VCCQ
GND
NC
V DQd
DQd
A
W DQd DQd TMS
Bd
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
A
A
TDI
NC
(128M)
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NC
NC
(64M)
A
A
E1
MCL
VCC
ZQ
EP2
EP3
M4
MCL
M2
M3
SD
MCL
VCC
MCL
A
A1
A0
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
7
A
(8M)
A
NC
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NC
NC
(32M)
A
A
8
E3
Bb
Be
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
A
A
TDO
9 10 11
A DQb DQb
Bf DQb DQb
Ba DQb DQb
GND
VCCQ
GND
VCCQ
GND
VCCQ
NC
VCCQ
GND
VCCQ
GND
VCCQ
GND
NC
DQb
DQPf
DQf
DQf
DQf
DQf
CQ1
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQb
DQPb
DQf
DQf
DQf
DQf
CQ1
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
A DQe DQe
TCK DQe DQe
2 Integrated Silicon Solution, Inc. 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01
Free Datasheet http://www.datasheet4u.com/



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IS61NSCS25672
IS61NSCS51236
ISSI ®
IS61NSCS51236 PINOUT
512K x 36 Common I/OTop View
1234
A NC
NC
A
E2
B NC NC Bc NC
C NC NC NC Bd
D NC
NC
E NC DQPc
F DQc
DQc
G DQc
DQc
H DQc
DQc
J DQc
K CQ2
DQc
CQ2
L NC
NC
M NC
NC
N NC
NC
P NC
NC
R DQPd
NC
T DQd DQd
U DQd
DQd
GND
VCCQ
GND
VCCQ
GND
VCCQ
CLK
VCCQ
GND
VCCQ
GND
VCCQ
GND
NC
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
A
V DQd
DQd
A
A
W DQd
DQd
TMS
TDI
5
A
(16M)
A
(x36)
NC
(128M)
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NC
NC
(64M)
A
A
6
ADV
W
E1
MCL
VCC
ZQ
EP2
EP3
M4
MCL
M2
M3
SD
MCL
VCC
MCL
A
A1
A0
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
7
A
A
NC
NC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
NC
NC
(32M)
A
A
8
E3
Bb
NC
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
VCCQ
GND
VCCQ
GND
VCCQ
NC
A
A
TDO
9 10 11
A DQb DQb
NC DQb DQb
Ba DQb DQb
GND
VCCQ
GND
VCCQ
GND
VCCQ
NC
VCCQ
GND
VCCQ
GND
VCCQ
GND
NC
DQb
NC
NC
NC
NC
NC
CQ1
DQa
DQa
DQa
DQa
DQPa
NC
NC
DQb
DQPb
NC
NC
NC
NC
CQ1
DQa
DQa
DQa
DQa
NC
NC
NC
A NC
TCK NC
NC
NC
Integrated Silicon Solution, Inc. 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01
3
Free Datasheet http://www.datasheet4u.com/



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IS61NSCS25672
IS61NSCS51236
ISSI ®
PIN DESCRIPTION TABLE
Symbol
A
A
ADV
Bx
Bx
Bx
CK
CQ
CQ
DQ
DQ
E1
E2 & E3
EP2 & EP3
TCK
TDI
TDO
TMS
M2, M3 & M4
SD
MCL
Pin Location
Description
A3, A5, A7, A9, B7, U4,
U6, U8, V3, V4, V5, V6,
V7, V8, V9, W5, W6, W7
Address
B5 Address
A6 Advance
B3, C9
Byte Write Enable
B8, C4
Byte Write Enable
B4, B9, C3, C8
Byte Write Enable
K3 Clock
K1, K11
Echo Clock
K2, K10
Echo Clock
E2, F1, F2, G1, G2, H1,
H2, J1, J2, L10, L11,
M10, M11, N10, N11,
P10, P11, R10
A10, A11, B10, B11,
C10, C11, D10, D11,
E11, R1, T1, T2, U1, U2,
V1, V2, W1, W2
Data I/O
Data I/O
A1, A2, B1, B2, C1, C2,
D1, D2, E1, E10, F10,
F11, G10, G11, H10,
H11, J10, J11, L1, L2,
M1, M2, N1, N2, P1, P2,
R2, R11, T10, T11, U10,
U11, V10, V11, W10,
W11
Data I/O
C6 Chip Enable
A4, A8
Chip Enable
G6, H6
Chip Enable Program Pin
W9 Test Clock
W4 Test Data In
W8 Test Data Out
W3 Test Mode Select
L6, M6, J6
Mode Control Pins
N6 Slow Down
B3, C9, D6, K6
P6, T6, W6
Must Connect Low
Type
Input
Input
Input
Input
Input
Input
Input
Output
Output
Input/Output
Input/Output
Input/Output
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Comments
x36 version
Active High
Active Low (all versions)
Active Low (x36 and x72 versions)
Active Low (x72 version only)
Active High
Active High
Active Low
x36, and x72 versions
x72 version only
Active Low
Programmable Active High or Low
Active High
Active Low
4 Integrated Silicon Solution, Inc. 1-800-379-4774
ADVANCE INFORMATION Rev. 00A
06/19/01
Free Datasheet http://www.datasheet4u.com/



IS61NSCS51236 datasheet pdf
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IS61NSCS51236 (IS61NSCS25672 / IS61NSCS51236) Synchronous SRAM IS61NSCS51236
Integrated Silicon Solution
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