IPG20N04S4L-07 Datasheet PDF - Infineon

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IPG20N04S4L-07
Infineon

Part Number IPG20N04S4L-07
Description Power Transistor
Page 9 Pages


IPG20N04S4L-07 datasheet pdf
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OptiMOS-T2 Power-Transistor
Features
• Dual N-channel Logic Level - Enhancement mode
• AEC Q101 qualified
• MSL1 up to 260°C peak reflow
• 175°C operating temperature
• Green Product (RoHS compliant)
• 100% Avalanche tested
IPG20N04S4L-07
Product Summary
V DS
R
4)
DS(on),max
ID
40 V
7.2 mW
20 A
PG-TDSON-8-4
Type
IPG20N04S4L-07
Package
Marking
PG-TDSON-8-4 4N04L07
Maximum ratings, at T j=25 °C, unless otherwise specified
Parameter
Symbol
Conditions
Continuous drain current
one channel active
I D T C=25 °C, V GS=10 V1)
Pulsed drain current2)
one channel active
Avalanche energy, single pulse2, 4)
Avalanche current, single pulse4)
Gate source voltage
Power dissipation
one channel active
T C=100 °C,
V GS=10 V2)
I D,pulse -
E AS
I AS
V GS
I D=10A
-
-
P tot T C=25 °C
Operating and storage temperature T j, T stg -
Value
20
20
80
230
15
±16
65
-55 ... +175
Unit
A
mJ
A
V
W
°C
Rev. 1.0
page 1
2010-10-05



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IPG20N04S4L-07
Parameter
Symbol
Conditions
Thermal characteristics2)
Thermal resistance, junction - case
SMD version, device on PCB
R thJC
R thJA
-
minimal footprint
6 cm2 cooling area3)
min.
Values
typ.
Unit
max.
- - 2.3 K/W
- 100 -
- 60 -
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
V (BR)DSS V GS=0 V, I D= 1 mA
40
-
-V
Gate threshold voltage
V GS(th) V DS=V GS, I D= 30µA 1.2 1.7 2.2
Zero gate voltage drain current4)
I DSS
V DS=40 V, V GS=0 V,
T j=25 °C
-
0.01
1 µA
Gate-source leakage current4)
Drain-source on-state resistance4)
V DS=18 V, V GS=0 V,
T j=85 °C2)
I GSS
V GS=16 V, V DS=0 V
R DS(on) V GS=4.5 V, I D=10 A
V GS=10 V, I D=17 A
-
-
-
-
1 100
- 100 nA
8.0 9.2 mW
6.5 7.2
Rev. 1.0
page 2
2010-10-05



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IPG20N04S4L-07
Parameter
Dynamic characteristics2)
Input capacitance4)
Output capacitance4)
Reverse transfer capacitance4)
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate Charge Characteristics2, 4)
Gate to source charge
Gate to drain charge
Gate charge total
Gate plateau voltage
Reverse Diode
Diode continous forward current2)
one channel active
Diode pulse current2)
one channel active
Diode forward voltage
Reverse recovery time2)
Symbol
Conditions
min.
Values
typ.
Unit
max.
C iss
C oss
Crss
t d(on)
tr
t d(off)
tf
V GS=0 V, V DS=25 V,
f =1 MHz
V DD=20 V, V GS=10 V,
I D=20 A, R G=11 W
-
-
-
-
-
-
-
3060
560
25
9
4
50
25
3980 pF
730
58
- ns
-
-
-
Q gs - 8.2 11 nC
Q gd V DD=32 V, I D=20 A,
Q g V GS=0 to 10 V
-
-
49
39 50
V plateau
- 2.7 - V
IS
I S,pulse
T C=25 °C
V SD
V GS=0 V, I F=17 A,
T j=25 °C
t rr
V R=20 V, I F=I S,
di F/dt =100 A/µs
- - 20 A
- - 80
- 0.9 1.3 V
- 36 - ns
Reverse recovery charge2, 4)
Q rr
- 34 - nC
1) Current is limited by bondwire; with an R thJC =2.3 K/W the chip is able to carry 73A at 25°C.
2) Specified by design. Not subject to production test.
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
4) Per channel
Rev. 1.0
page 3
2010-10-05



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IPG20N04S4L-07
1 Power dissipation
P tot = f(T C); V GS ≥ 6 V; one channel active
2 Drain current
I D = f(T C); V GS ≥ 6 V; one channel active
70 25
60
20
50
15
40
30
10
20
5
10
00
0 50 100 150 200
0 50 100 150
T C [°C]
T C [°C]
3 Safe operating area
I D=f(V DS); T C=25°C; D =0; one channel active
parameter: t p
100
10 µs
1 µs
4 Max. transient thermal impedance
Z thJC = f(t p)
parameter: D =t p/T
101
100 µs
10 100 0.5
200
1
0.1
0.1
Rev. 1.0
1 ms
1 10
V DS [V]
100
0.1
0.05
10-1
0.01
single pulse
10-2
10-6
10-5
10-4
10-3
10-2
10-1
100
t p [s]
page 4
2010-10-05



IPG20N04S4L-07 datasheet pdf
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