IDTCV145 Datasheet PDF - Integrated Device Technology

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IDTCV145
Integrated Device Technology

Part Number IDTCV145
Description CLOCK BUFFER
Page 13 Pages


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IDTCV145
1-TO-19DIFFERENTIALCLOCKBUFFER
1-TO-19 DIFFERENTIAL
CLOCK BUFFER
COMMERCIALTEMPERATURERANGE
IDTCV145
FEATURES:
• Compliant with Intel DB1900G
• DIF Clock Support
19 differential clock output pairs @ 0.7 V
150 ps skew performance across all outputs
• OE pin Control of All Outputs
• 3.3 V Operation
• Gear Ratio supporting generation of clocks at a different
frequency ratioed from the input.
• Split outputs supporting options of 2 outputs @1:1 and
remaining 17 pairs at an alternate gear
• Pin level OE control of individual outputs
• Multiple output frequency options up to 400Mhz as a gear ratio
of input clocks of 100-400Mhz
• Output is HCSL compatible
• SMBus Programmable configurations
• PLL Bypass Configurable
• SMBus address configurable to allow multiple buffer control in
a single control network
• Programmable Bandwidth
• Glitchfree transition between frequency states
• Available in 72-pin VFQPFN package
DESCRIPTION:
The CV145 differential buffer complies with Intel DB1900G , and is designed
to work in conjunction with the main clock of CK409, CK410/CK410M and
CK410B etc., PLL is off in bypass mode and no clock detect.
FUNCTIONAL BLOCK DIAGRAM
OE_17_18#
OE[16:5]#
OE_01234#
PD#
Output
Control
SCL
SDA
SA_2/PLL_BYPASS#
CLK_IN
CLK_IN#
HIGH_BW#
SM Bus
Controller
PLL
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
© 2005 Integrated Device Technology, Inc.
1
Output
Buffer
DIF_0
DIF_0#
DIF_1
DIF_1#
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
DIF_5
DIF_5#
DIF_6
DIF_6#
DIF_18
DIF_18#
JUNE 2006
DSC-6753/14
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IDTCV145
1-TO-19DIFFERENTIALCLOCKBUFFER
PIN CONFIGURATION
COMMERCIALTEMPERATURERANGE
IREF
VSS
PD#
HIGH_BW#
FSA
DIF_0
DIF_0#
DIF_1
DIF_1#
VSS
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
OE_01234#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
54 OE_14#
53 DIF_13#
52 DIF_13
51 OE_13#
50 DIF_12#
49 DIF_12
48 OE_12#
47 VDD
46 VSS
45 DIF_11#
44 DIF_11
43 OE_11#
42 DIF_10#
41 DIF_10
40 OE_10#
39 DIF_9#
38 DIF_9
37 OE_9#
VFQFPN
TOP VIEW
2
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IDTCV145
1-TO-19DIFFERENTIALCLOCKBUFFER
COMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Min. Max.
VDDA 3.3V Core Supply Voltage
4.6
VDDIN
3.3V Logic Input Supply Voltage GND - 0.5
4.6
TSTG Storage Temperature
–65 +150
TAMBIENT Ambient Operating Temperature
0
+70
TCASE
Case Temperature
+115
ESD Prot Input ESD Protection
2000
Human Body Model
Unit
V
V
°C
°C
°C
V
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OE FUNCTIONALITY
OE# - Pin
0
0
1
1
OE# - SMBus bit
1
0
1
0
DIF
Normal
Tristate
Tristate
Tristate
PD FUNCTIONALITY
Inputs
PD# / VDDA CLK_IN / CLK_IN#
3.3V (Nom)
Running
GND X
Outputs
DIF DIF#
Running
Hi-Z
DIFF]#
Normal
Tristate
Tristate
Tristate
PLL State
ON
OFF
PIN DESCRIPTION
Pin Name
Type
CLK_IN, CLK_IN#
IN
DIF_[16:0] & DIF_[16:0]#
OUT
DIF & DIF# [18:17]
OE_[16:5]#
OE _17_18#
OE_01234#
HIGH_BW#
SCL
SDA
IREF
SA_[1:0]
SA_2/PLL_BYPASS#
FS_A
PD#
OUT
IN
IN
IN
IN
IN
I/O, OC
IN
IN
IN
IN
IN
Pin #
70, 71
6 - 9, 12 - 17, 22, 23, 25,
26, 30, 31, 33, 34, 38, 39,
41, 42, 44, 45, 49, 50, 52,
53, 55, 56, 58, 59, 61, 62
65 - 68
21, 24, 29, 32, 37, 40, 43,
48, 51, 54, 57, 60
69
18
4
19
20
1
35, 36
72
5
3
Description
0.7v Differential input
0.7 V Differential clock outputs, geared to a ratio of the input clock
0.7 V Differential clock outputs, which can be configured to be 1:1 instead of geared. Default
is geared same as 0-9 outputs.
3.3 V LVTTL active LOW input for enabling corresponding differential output clock. Clocks
also can be disabled via SMBus registers
3.3VLVTTLactivelowinputforenablingboth DIF10and11differentialoutputclocks.Clocks
also can be disabled via SMBus registers individually.
3.3V LVTTL input
3.3 V LVTTL input for selecting the PLL bandwidth. 0 = HIGH BW, 1 = LOW BW.
SMBus slave clock input
Open collector SMBus data
A precision resistor is attached to this pin to set the differential output current
3.3V LVTTL input selecting the address. SA_[2:0] set device SMBus address.
3.3 V LVTTL input for PLLbypass and SMBus address
3.3V LVTTL input to establish a HIGH (>200Mhz) or LOW frequency(<200Mhz) range
3.3 V LVTTL input to power up or power down the device (see PD Functionality table).
3
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IDTCV145
1-TO-19DIFFERENTIALCLOCKBUFFER
INDEX BLOCK WRITE PROTOCOL
Bit # of bits From
Description
1 1 Master Start
2-9 8 Master See SMBus Address Mode table
10 1 Slave Ack (Acknowledge)
11-18 8 Master Register offset byte (starting byte)
19 1 Slave Ack (Acknowledge)
20-27 8 Master Byte count, N (0 is not valid)
28 1 Slave Ack (Acknowledge)
29-36 8 Master first data byte (Offset data byte)
37 1 Slave Ack (Acknowledge)
38-45 8 Master 2nd data byte
46 1 Slave Ack (Acknowledge)
:
Master
Slave
Nth data byte
Acknowledge
Master
Stop
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
COMMERCIALTEMPERATURERANGE
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
Bit # of bits
11
2-9 8
10 1
11-18 8
19 1
20 1
21-28 8
29 1
30-37 8
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
38 1
39-46 8
47 1
48-55 8
Master
Slave
Master
Slave
Master
Slave
Master
Description
Start
See SMBus Address Mode table
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
See SMBus Address Mode table
Ack (Acknowledge)
Byte count, N (block read back of N
bytes)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
4
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