ICS952801 Datasheet PDF - Integrated Circuit Systems

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ICS952801
Integrated Circuit Systems

Part Number ICS952801
Description Programmable Timing Control HubTM for K8TM processor
Page 22 Pages


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Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
Programmable Timing Control Hub™ for K8™ processor
Recommended Application:
SiS755/760 style chipset for AMD K8 Processor
Output Features:
• 2 - Pairs of differential push-pull K8CPU outputs
• 8 - PCICLK @ 3.3V
• 2 - AGPCLK @ 3.3V
• 3 - REF @ 3.3V
• 2 - ZCLK @ 3.3V
• 1 - 24_48MHz @ 3.3V
• 1 - 48MHz @ 3.3V
Key Specifications:
• CPU Output Jitter <250ps
• AGP Output Jitter <250ps
• ZCLK Output Jitter <250ps
• PCI Output Jitter <500ps
Functionality
Bit4 Bit3 Bit2 Bit1 Bit0 CPU ZCLK AGP
FS4 FS3 FS2 FS1 FS0 MHz MHz MHz
0 0 0 0 0 200.00 66.67 66.67
0 0 0 0 1 200.00 100.00 66.67
0 0 0 1 0 200.00 133.33 66.67
0 0 0 1 1 200.00 166.67 66.67
0 0 1 0 0 233.33 66.67 66.67
0 0 1 0 1 233.33 93.33 66.67
0 0 1 1 0 233.33 133.33 66.67
0 0 1 1 1 233.33 175.00 70.00
0 1 0 0 0 266.67 66.67 66.67
0 1 0 0 1 266.67 106.67 66.67
0 1 0 1 0 266.67 133.33 66.67
0 1 0 1 1 266.67 160.00 66.67
0 1 1 0 0 293.34 73.34 73.33
0 1 1 0 1 293.34 117.34 73.33
0 1 1 1 0 293.34 146.66 73.33
0 1 1 1 1 293.34 176.00 73.33
1 0 0 0 0 133.33 66.67 66.67
1 0 0 0 1 133.33 100.00 66.67
1 0 0 1 0 133.33 133.33 66.67
1 0 0 1 1 133.33 166.67 66.67
1 0 1 0 0 166.67 66.67 66.67
1 0 1 0 1 166.67 100.00 66.67
1 0 1 1 0 166.67 133.33 66.67
1 0 1 1 1 166.67 166.67 66.67
1 1 0 0 0 202.00 67.34 67.33
1 1 0 0 1 202.00 101.00 67.33
1 1 0 1 0 202.00 134.66 67.33
1 1 0 1 1 202.00 168.34 67.33
1 1 1 0 0 220.00 73.34 73.33
1 1 1 0 1 220.00 110.00 73.33
1 1 1 1 0 220.00 146.66 73.33
1 1 1 1 1 220.00 183.34 73.33
Features/Benefits:
• QuadRomTM frequency selection.
• Selectable synchronous/asynchronous AGP/PCI/ZCLK
frequency
• Linear Programmable CPU output frequency.
• Linear Programmable AGP/PCI output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system if system
malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz referience input.
Pin Configuration
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
35.00
33.33
33.33
33.33
33.33
36.66
36.66
36.66
36.66
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
36.66
36.66
36.66
36.66
VDDREF 1
48 CPU_STOP#*
**FS0/REF0 2
47 GNDCPU
**FS1/REF1 3
46 CPUCLK8T1
**FS2/REF2 4
GNDREF 5
45 CPUCLK8C1
44 VDDCPU
X1 6
43 VDDCPU
X2 7
42 CPUCLK8T0
GNDZ 8
41 CPUCLK8C0
ZCLK0 9
ZCLK1 10
40 GNDCPU
39 AGND
VDDZ 11
*PCI_STOP# 12
**FS3/PCICLK_F0 13
**FS4/PCICLK_F1 14
VDDPCI 15
GNDPCI 16
PCICLK0 17
PCICLK1 18
PCICLK2 19
PCICLK3 20
PCICLK4 21
PCICLK5 22
38 AVDD
37 PD#*
36 GNDAGP
35 AGPCLK0
34 AGPCLK1
33 VDDAGP
32 SCLK
31 AVDD48
30 48MHz
29 24_48MHz/SEL24_48MHz*
28 GND48
27 SDATA
GNDPCI 23
26 PCICLK7
VDDPCI 24
25 PCICLK6
48-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
0719—01/22/03
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.



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Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
General Description
The ICS952801 is a two chip clock solution for desktop designs using SIS 755/760 style chipsets. When used with a zero
delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks
signals for such a system.
The ICS952801 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
X1 XTAL
X2
PLL2
Frequency
Dividers
PD#
CPU_STOP#
PCI_STOP#
FS (4:0)
SEL24_48MHZ
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz
24_48MHz
REF (2:0)
CPUCLK8T (1:0)
CPUCLK8C (1:0)
AGPCLK (1:0)
PCICLK (5:0)
PCICLKF (1:0)
ZCLK (1:0)
Power Groups
Pin Number
VDD
GND
15
31 28
38 36
Description
REF Output, Crystal
24/48MHz, Fix Analog, Fix Digital
CPU PLL, CPU Analog, MCLK
0719—01/22/03
2



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Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
Pin Description
PIN PIN
# NAME
PIN
TYPE
DESCRIPTION
1 VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
2 **FS0/REF0
I/O Frequency select latch input pin / 14.318 MHz reference clock.
3 **FS1/REF1
I/O Frequency select latch input pin / 14.318 MHz reference clock.
4 **FS2/REF2
I/O Frequency select latch input pin / 14.318 MHz reference clock.
5 GNDREF
PWR Ground pin for the REF outputs.
6 X1
IN Crystal input,nominally 14.318MHz.
7 X2
OUT Crystal output, Nominally 14.318MHz
8 GNDZ
PWR Ground pin for the ZCLK outputs
9 ZCLK0
OUT 3.3V Hyperzip clock output.
10 ZCLK1
OUT 3.3V Hyperzip clock output.
11 VDDZ
PWR Power supply for ZCLK clocks, nominal 3.3V
12 *PCI_STOP#
I/O
PCI clock output, this output is activated by the Mode selection pin / Stops all PCICLKs
besides the PCICLK_F clocks at logic 0 level, when input low.
13 **FS3/PCICLK_F0
I/O Frequency select latch input pin / 3.3V PCI free running clock output.
14 **FS4/PCICLK_F1
I/O Frequency select latch input pin / 3.3V PCI free running clock output.
15 VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
16 GNDPCI
PWR Ground pin for the PCI outputs
17 PCICLK0
OUT PCI clock output.
18 PCICLK1
OUT PCI clock output.
19 PCICLK2
OUT PCI clock output.
20 PCICLK3
OUT PCI clock output.
21 PCICLK4
OUT PCI clock output.
22 PCICLK5
OUT PCI clock output.
23 GNDPCI
PWR Ground pin for the PCI outputs
24 VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
25 PCICLK6
OUT PCI clock output.
26 PCICLK7
OUT PCI clock output.
27 SDATA
I/O Data pin for I2C circuitry 5V tolerant
28 GND48
PWR Ground pin for the 48MHz outputs
29 24_48MHz/SEL24_48MHz*
I/O
24/48MHz clock output / Latched select input for 24/48MHz output. 0=24mHz, 1 =
48MHz.
30 48MHz
OUT 48MHz clock output.
31 AVDD48
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
32 SCLK
IN Clock pin of I2C circuitry 5V tolerant
33 VDDAGP
PWR Power supply for AGP clocks, nominal 3.3V
34 AGPCLK1
OUT AGP clock output
35 AGPCLK0
OUT AGP clock output
36 GNDAGP
PWR Ground pin for the AGP outputs
Asynchronous active low input pin used to power down the device into a low power
37 PD#*
IN state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 1.8ms.
38 AVDD
PWR 3.3V Analog Power pin for Core PLL
39 AGND
PWR Analog Ground pin for Core PLL
40 GNDCPU
PWR Ground pin for the CPU outputs
41 CPUCLK8C0
OUT "Complementary" clocks of differential 3.3V push-pull K8 pair.
42 CPUCLK8T0
OUT "True" clocks of differential 3.3V push-pull K8 pair.
43 VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
44 VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
45 CPUCLK8C1
OUT "Complementary" clocks of differential 3.3V push-pull K8 pair.
46 CPUCLK8T1
OUT "True" clocks of differential 3.3V push-pull K8 pair.
47 GNDCPU
PWR Ground pin for the CPU outputs
48 CPU_STOP#*
IN Stops all CPUCLK besides the free running clocks
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
0719—01/22/03
3



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Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
General I2C serial interface information for the ICS952801
How to Write:
Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each
byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address D3(H)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P stoP bit
Byte N + X - 1
0719—01/22/03
4



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