ICS952702 Datasheet PDF - Integrated Circuit Systems

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ICS952702
Integrated Circuit Systems

Part Number ICS952702
Description Programmable Timing Control Hub for K7 System
Page 17 Pages


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Integrated
Circuit
Systems, Inc.
ICS952702
Programmable Timing Control Hub for K7TM System
Recommended Application:
SiS746/746FX style chipset
Output Features:
• 1 - Pair of differential open drain CPU outputs
• 1 - Single-ended open drain CPU output
• 8 - PCICLK @ 3.3V including 2 PCI clock free running
• 2 - AGPCLK @ 3.3V
• 3 - REF @ 3.3V
• 2 - ZCLK @ 3.3V
• 2 - IOAPIC @ 2.5V
• 1 - 12_48MHz @ 3.3V
• 1 - 24_48MHz @ 3.3V
Key Specifications:
• CPU Output Jitter <250ps
• AGP Output Jitter <250ps
• ZCLK Output Jitter <250ps
• PCI Output Jitter <500ps
• CPU-AGP/PCI/ZCLK skew: 2.5ns~3.5ns
Features/Benefits:
• Selectable synchronous/asynchronous AGP/PCI
frequency
• Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz reference or XTAL input.
Pin Configuration
Functionality
VDDREF 1
48 VDDLAPIC
**FS0/REF0 2
47 IOAPIC1
**FS1/REF1 3
46 IOAPIC0
**FS4/REF2 4
45 GNDAPIC
GNDREF 5
44 CPU_STOP#*
X1 6
43 CPUCLKODT1
X2 7
42 RESET#
GNDZ 8
41 GNDCPU
ZCLK0 9
40 CPUCLKODT0
ZCLK1 10
39 CPUCLKODC0
VDDZ 11
38 VDDCPU
*PCI_STOP# 12
37 AGND
VDDPCI 13
36 AVDD
**FS2/PCICLK_F0 14
35 SCLK
*FS3/PCICLK_F1 15
34 SDATA
PCICLK0 16
33 PD#*
PCICLK1 17
GNDPCI 18
32 GNDAGP
31 AGPCLK0
VDDPCI 19
30 AGPCLK1
PCICLK2 20
29 VDDAGP
PCICLK3 21
28 AVDD48
PCICLK4 22
27 12_48MHz/SEL12#_48MHz*
PCICLK5 23
26 24_48MHz/SEL24#_48MHz**
GNDPCI 24
25 GND48
48-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
0795D—05/06/05
Bit4 Bit3 Bit2 Bit1 Bit0 CPU ZCLK AGP
FS4 FS3 FS2 FS1 FS0 MHz MHz MHz
0 0 0 0 0 200.00 133.33 66.67
0 0 0 0 1 200.99 133.99 67.00
0 0 0 1 0 200.00 66.67 66.67
0 0 0 1 1 206.00 137.33 68.67
0 0 1 0 0 133.33 133.33 66.67
0 0 1 0 1 214.00 142.66 71.33
0 0 1 1 0 218.00 145.33 72.67
0 0 1 1 1 222.00 148.00 74.00
0 1 0 0 0 100.00 133.33 66.67
0 1 0 0 1 100.99 134.65 67.33
0 1 0 1 0 100.00 66.67 66.67
0 1 0 1 1 103.00 137.33 68.67
0 1 1 0 0 100.00 133.33 66.67
0 1 1 0 1 107.00 142.66 71.33
0 1 1 1 0 109.00 145.33 72.67
0 1 1 1 1 111.00 148.00 74.00
1 0 0 0 0 166.67 133.33 66.67
1 0 0 0 1 166.99 133.59 66.80
1 0 0 1 0 166.67 66.67 66.67
1 0 0 1 1 171.67 137.33 68.67
1 0 1 0 0 175.00 140.00 70.00
1 0 1 0 1 178.34 142.66 71.33
1 0 1 1 0 181.67 145.33 72.67
1 0 1 1 1 185.00 148.00 74.00
1 1 0 0 0 133.33 133.33 66.67
1 1 0 0 1 133.99 133.99 67.00
1 1 0 1 0 133.33 66.67 66.67
1 1 0 1 1 137.33 137.33 68.67
1 1 1 0 0 140.00 140.00 70.00
1 1 1 0 1 142.66 142.66 71.33
1 1 1 1 0 145.33 145.33 72.67
1 1 1 1 1 148.00 148.00 74.00
PCI
MHz
33.33
33.50
33.33
34.33
33.33
35.67
36.33
37.00
33.33
33.66
33.33
34.33
33.33
35.67
36.33
37.00
33.33
33.40
33.33
34.33
35.00
35.67
36.33
37.00
33.33
33.50
33.33
34.33
35.00
35.67
36.33
37.00



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Integrated
Circuit
Systems, Inc.
ICS952702
General Description
The ICS952702 is a two chip clock solution for desktop designs using SIS 746 style chipsets. When used with a zero delay
buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals
for such a system.
The ICS952702 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
X1 XTAL
X2
CPU_STOP#
PCI_STOP#
SCLK
SEL24_48MHZ
SEL12_48
PD#
SDATA
FS (4:0)
Control
Logic
PLL2
Frequency
Dividers
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
12_48MHZ
24_48MHZ
REF (2:0)
CPUCLKODT (1:0)
CPUCLKODC0
RESET#
IOAPIC (1:0)
PCICLKF (1:0)
PCICLK (5:0)
ZCLK (1:0)
AGPCLK (1:0)
Power Groups
Pin Number
VDD
GND
15
11 8
28 25
13,19
18,24
29 32
48 45
38 41
36 37
Description
REF output, Xtal
Hyper ZCLK output
24/48MHz fixed, Fixed PLL (Fix1)
PCICLK output
AGP output
IOAPIC output
CPU_T/C output
CPU PLL, CPU MCLK
0795D—05/06/05
2



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Integrated
Circuit
Systems, Inc.
ICS952702
Pin Description
PIN #
PIN NAME
1 VDDREF
2 **FS0/REF0
3 **FS1/REF1
4 **FS4/REF2
5 GNDREF
6 X1
7 X2
8 GNDZ
9 ZCLK0
10 ZCLK1
11 VDDZ
12 *PCI_STOP#
13 VDDPCI
14 **FS2/PCICLK_F0
15 *FS3/PCICLK_F1
16 PCICLK0
17 PCICLK1
18 GNDPCI
19 VDDPCI
20 PCICLK2
21 PCICLK3
22 PCICLK4
23 PCICLK5
24 GNDPCI
25 GND48
26 24_48MHz/SEL24#_48MHz**
27 12_48MHz/SEL12#_48MHz*
28 AVDD48
29 VDDAGP
30 AGPCLK1
31 AGPCLK0
32 GNDAGP
33 PD#*
34 SDATA
35 SCLK
36 AVDD
37 AGND
38 VDDCPU
39 CPUCLKODC0
40 CPUCLKODT0
41 GNDCPU
42 RESET#
43 CPUCLKODT1
44 CPU_STOP#*
45 GNDAPIC
46 IOAPIC0
47 IOAPIC1
48 VDDLAPIC
* Internal Pull-Up Resistor
PIN
TYPE
DESCRIPTION
PWR Ref, XTAL power supply, nominal 3.3V
I/O Frequency select latch input pin / 14.318 MHz reference clock.
I/O Frequency select latch input pin / 14.318 MHz reference clock.
I/O Frequency select latch input pin / 14.318 MHz reference clock.
PWR Ground pin for the REF outputs.
IN Crystal input, Nominally 14.318MHz.
OUT Crystal output, Nominally 14.318MHz
PWR Ground pin for the ZCLK outputs
OUT 3.3V Hyperzip clock output.
OUT 3.3V Hyperzip clock output.
PWR Power supply for ZCLK clocks, nominal 3.3V
IN Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low.
PWR Power supply for PCI clocks, nominal 3.3V
I/O Frequency select latch input pin / 3.3V PCI free running clock output.
I/O Frequency select latch input pin / 3.3V PCI free running clock output.
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin for the PCI outputs
PWR Power supply for PCI clocks, nominal 3.3V
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin for the PCI outputs
PWR Ground pin for the 48MHz outputs
I/O Selectable 24 or 48MHz clock output / Latched select input for 24/48MHz output. 0=24MHz,
1 = 48MHz.
Selectable 12 or 48MHz clock output / Latched select input for 12/48MHz output. 0=12MHz,
I/O 1 = 48MHz.
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
PWR Power supply for AGP clocks, nominal 3.3V
OUT AGP clock output
OUT AGP clock output
PWR Ground pin for the AGP outputs
Asynchronous active low input pin used to power down the device into a low power state. The
IN internal clocks are disabled and the VCO and the crystal are stopped. The latency of the
power down will not be greater than 1.8ms.
I/O Data pin for I2C circuitry 5V tolerant
IN Clock pin of I2C circuitry 5V tolerant
PWR 3.3V Analog Power pin for Core PLL
PWR Analog Ground pin for Core PLL
PWR Supply for CPU clocks, 3.3V nominal
OUT
OUT
"Complememtary" clocks of differential pair CPU outputs. These open drain outputs need an
external 1.5V pull-up.
True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V
pull-up.
PWR Ground pin for the CPU outputs
OUT
OUT
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V
pull-up.
IN Stops all CPUCLK besides the free running clocks
PWR Ground pin for the IOAPIC outputs.
OUT IOAPIC clock outputs, norminal 2.5V.
OUT IOAPIC clock outputs, norminal 2.5V.
PWR Power pin for the IOAPIC outputs. 2.5V.
** Internal Pull-Down Resistor
0795D—05/06/05
3



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Integrated
Circuit
Systems, Inc.
ICS952702
General SMBus serial interface information for the ICS952702
How to Write:
Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each
byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address D3(H)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P stoP bit
Byte N + X - 1
0795D—05/06/05
4



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