ICS952606 Datasheet PDF - Integrated Circuit Systems

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ICS952606
Integrated Circuit Systems

Part Number ICS952606
Description Programmable Timing Control Hub for Next Gen P4 processor
Page 20 Pages


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Integrated
Circuit
Systems, Inc.
ICS952606
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK409 48-pin part
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential CPU pairs for ITP
• 1 - 0.7V current-mode differential SRC pair
• 9 - PCI (33MHz)
• 1 - USB, 48MHz
• 1 - DOT, 48MHz
• 2 - REF, 14.318MHz
• 3 - 3V66, 66.66MHz
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA
• Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
• Supports CPU clks up to 400MHz in test mode
• Uses external 14.318MHz crystal
• Supports undriven differential CPU, SRC pair in PD#
for power management.
• 1 - 3V66/VCH, selectable 48MHz or 66MHz
Key Specifications:
• CPU/SRC outputs cycle-cycle jitter < 125ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 250ps
• CPU outputs skew: < 100ps
Pin Configuration
*FSA/REF0 1
*FSB/REF1 2
VDDREF 3
• +/- 300ppm frequency accuracy on CPU & SRC clocks
X1 4
X2 5
GND 6
Functionality
PCICLK_F0 7
PCICLK_F1 8
FS2 CPU SRC
B6b5 FS_A FS_B MHz MHz
0 0 100.00 100/200
0
0
1
1 200.00 100/200
0 133.33 100/200
1 1 166.66 100/200
0 0 200.00 100/200
1
0
1
1 400.00 100/200
0 266.66 100/200
1 1 333.33 100/200
3V66
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
REF
MHz
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
USB/
DOT
MHz
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
PCICLK_F2 9
VDDPCI 10
GND 11
PCICLK0 12
PCICLK1 13
PCICLK2 14
PCICLK3 15
VDDPCI 16
GND 17
PCICLK4 18
PCICLK5 19
PD# 20
48MHz_DOT 21
48MHz_USB 22
GND 23
VDD48 24
48 VDDA
47 GND
46 IREF
45 CPUCLKT_ITP
44 CPUCLKC_ITP
43 GND
42 CPUCLKT1
41 CPUCLKC1
40 VDDCPU
39 CPUCLKT0
38 CPUCLKC0
37 GND
36 SRCCLKT
35 SRCCLKC
34 VDD
33 Vtt_Pwrgd#
32 SDATA
31 SCLK
30 3V66_0
29 3V66_1
28 GND
27 VDD3V66
26 3V66_2
25 3V66_3/VCH
**120KW pull-down
48-pin SSOP
0717F—06/10/05



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Integrated
Circuit
Systems, Inc.
Pin Description
PIN #
PIN NAME
1 *FSA/REF0
2 *FSB/REF1
3 VDDREF
4 X1
5 X2
6 GND
7 PCICLK_F0
8 PCICLK_F1
9 PCICLK_F2
10 VDDPCI
11 GND
12 PCICLK0
13 PCICLK1
14 PCICLK2
15 PCICLK3
16 VDDPCI
17 GND
18 PCICLK4
19 PCICLK5
20 PD#
21 48MHz_DOT
22 48MHz_USB
23 GND
24 VDD48
ICS952606
PIN TYPE
DESCRIPTION
I/O
I/O
PWR
IN
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
PWR
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Asynchronous active low input pin, with 120Kohm internal pull-up
resistor, used to power down the device. The internal clocks are
disabled and the VCO and the crystal are stopped.
48MHz clock output.
48MHz clock output.
Ground pin.
Power pin for the 48MHz output.3.3V
0717F—06/10/05
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Integrated
Circuit
Systems, Inc.
ICS952606
Pin Description (Continued)
PIN #
PIN NAME
30 3V66_0
25 3V66_3/VCH
26 3V66_2
27 VDD3V66
28 GND
29 3V66_1
30 3V66_0
31 SCLK
32 SDATA
33 Vtt_Pwrgd#
34 VDD
35 SRCCLKC
36 SRCCLKT
37 GND
38 CPUCLKC0
39 CPUCLKT0
40 VDDCPU
41 CPUCLKC1
42 CPUCLKT1
43 GND
44 CPUCLKC_ITP
45 CPUCLKT_ITP
46 IREF
47 GND
48 VDDA
PIN TYPE
DESCRIPTION
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
IN
PWR
OUT
OUT
PWR
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output / 48MHz VCH clock output.
3.3V 66.66MHz clock output
Power pin for the 3.3V 66MHz clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
Power supply, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
OUT
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
OUT
PWR
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
OUT
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
OUT
PWR
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
OUT
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
OUT
OUT
PWR
PWR
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin.
3.3V power for the PLL core.
0717F—06/10/05
3



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Integrated
Circuit
Systems, Inc.
ICS952606
General Description
ICS952606 is a 48 pin clock chip following Intel CK409 Yellow Cover specification. This clock synthesizer provides a single
chip solution for next generation P4 Intel processors and Intel chipsets. ICS952606 is driven with a 14.318MHz crystal. It
generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
Block Diagram
X1 XTAL
X2
PLL2
Frequency
Dividers
SCLK
SDATA
VTTPWRGD#
PD#
FS_A
FS_B
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz, USB, DOT, VCH
REF (1:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
SRCCLKT0
SRCCLKC0
3V66(3:0)
PCICLK_F (2:0)
PCICLK (5:0)
CPUCLKT_ITP
CPUCLKC_ITP
I REF
Power Groups
Pin Number
VDD
GND
36
27 28
10,16
11,17
34 37
48 47
24 23
-- 47
40 43
Description
Xtal, Ref
3V66 [0:3]
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
48MHz, Fix Digital, Fix Analog
IREF
CPUCLK clocks
0717F—06/10/05
4



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