ICS952601 Datasheet PDF - Integrated Circuit Systems

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ICS952601
Integrated Circuit Systems

Part Number ICS952601
Description Programmable Timing Control Hub for Next Gen P4 processor
Page 24 Pages


ICS952601 datasheet pdf
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Integrated
Circuit
Systems, Inc.
ICS952601
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK409 clock, Intel Yellow Cover part
Output Features:
• 3 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential SRC pair
• 7 - PCI (33MHz)
• 3 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 48MHz
• 2 - REF, 14.318MHz
• 4 - 3V66, 66.66MHz
• 1 - VCH/3V66, selectable 48MHz or 66MHz
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA.
• Supports spread spectrum modulation, 0 to -0.5%
down spread.
• Supports CPU clks up to 400MHz in test mode.
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning.
• Supports undriven differential CPU, SRC pair in PD#
and CPU_STOP# for power management.
Key Specifications:
• CPU/SRC outputs cycle-cycle jitter < 125ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 250ps
• CPU outputs skew: < 100ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
Functionality
CPU
B6b5 FS_A FS_B MHz
0 0 100
0 MID Ref/N0
0 0 1 200
1 0 133
1 1 166
1 MID Hi-Z
0 0 200
1
0
1
1 400
0 266
1 1 333
SRC
MHz
100/200
Ref/N1
100/200
100/200
100/200
Hi-Z
100/200
100/200
100/200
100/200
3V66 PCI
MHz MHz
66.66 33.33
Ref/N2 Ref/N3
66.66 33.33
66.66 33.33
66.66 33.33
Hi-Z Hi-Z
66.66 33.33
66.66 33.33
66.66 33.33
66.66 33.33
REF
MHz
14.318
Ref/N4
14.318
14.318
14.318
Hi-Z
14.318
14.318
14.318
14.318
USB/DOT
MHz
48.00
Ref/N5
48.00
48.00
48.00
Hi-Z
48.00
48.00
48.00
48.00
Pin Configuration
REF0 1
REF1 2
VDDREF 3
X1 4
X2 5
GND 6
PCICLK_F0 7
PCICLK_F1 8
PCICLK_F2 9
VDDPCI 10
GND 11
PCICLK0 12
PCICLK1 13
PCICLK2 14
PCICLK3 15
VDDPCI 16
GND 17
PCICLK4 18
PCICLK5 19
PCICLK6 20
PD# 21
3V66_0 22
3V66_1 23
VDD3V66 24
GND 25
3V66_2 26
3V66_3 27
SCLK 28
56 FS_B
55 VDDA
54 GNDA
53 GND
52 IREF
51 FS_A
50 CPU_STOP#
49 PCI_STOP#
48 VDDCPU
47 CPUCLKT2
46 CPUCLKC2
45 GND
44 CPUCLKT1
43 CPUCLKC1
42 VDDCPU
41 CPUCLKT0
40 CPUCLKC0
39 GND
38 SRCCLKT
37 SRCCLKC
36 VDD
35 Vtt_PWRGD#
34 VDD48
33 GND
32 48MHz_DOT
31 48MHz_USB
30 SDATA
29 3V66_4/VCH
56-pin SSOP & TSSOP
0701G—10/13/04



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Integrated
Circuit
Systems, Inc.
ICS952601
Pin Description
PIN #
PIN NAME
1 REF0
2 REF1
3 VDDREF
4 X1
5 X2
6 GND
7 PCICLK_F0
8 PCICLK_F1
9 PCICLK_F2
10 VDDPCI
11 GND
12 PCICLK0
13 PCICLK1
14 PCICLK2
15 PCICLK3
16 VDDPCI
17 GND
18 PCICLK4
19 PCICLK5
20 PCICLK6
21 PD#
22 3V66_0
23 3V66_1
24 VDD3V66
25 GND
26 3V66_2
27 3V66_3
28 SCLK
PIN TYPE
DESCRIPTION
OUT
OUT
PWR
IN
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
14.318 MHz reference clock.
14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 1.8ms. Internal pull-up of 150K nominal.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of SMBus circuitry, 5V tolerant.
0701G—10/13/04
2



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Integrated
Circuit
Systems, Inc.
ICS952601
Pin Description (Continued)
PIN #
PIN NAME
29 3V66_4/VCH
30 SDATA
31 48MHz_USB
32 48MHz_DOT
33 GND
34 VDD48
35 Vtt_PWRGD#
36 VDD
37 SRCCLKC
38 SRCCLKT
39 GND
40 CPUCLKC0
41 CPUCLKT0
42 VDDCPU
43 CPUCLKC1
44 CPUCLKT1
45 GND
46 CPUCLKC2
47 CPUCLKT2
48 VDDCPU
49 PCI_STOP#
50 CPU_STOP#
51 FS_A
52 IREF
53 GND
54 GNDA
55 VDDA
56 FS_B
0701G—10/13/04
PIN TYPE
DESCRIPTION
OUT
I/O
OUT
OUT
PWR
PWR
IN
PWR
OUT
OUT
PWR
66.66MHz clock output for AGP support. AGP-PCI should be aligned
with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
Data pin for SMBus circuitry, 5V tolerant.
48MHz clock output.
48MHz clock output.
Ground pin.
Power pin for the 48MHz output.3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
Power supply for SRC clocks, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
OUT
PWR
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
OUT
PWR
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
OUT
PWR
IN
IN
IN
OUT
PWR
PWR
PWR
IN
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at logic
0 level, when input low. PCI and SRC clocks can be set to
Free_Running through I2C. Internal pull-up of 150K nominal.
Stops all CPUCLK besides the free running clocks. Internal pull-up of
150K nominal
Frequency select pin, see Frequency table for functionality
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin.
Ground pin for core.
3.3V power for the PLL core.
Frequency select pin, see Frequency table for functionality
3



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Integrated
Circuit
Systems, Inc.
ICS952601
General Description
ICS952601 follows Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS952601 is driven with a 14.318MHz crystal. It generates CPU outputs up
to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
Block Diagram
X1 XTAL
X2
PLL2
Frequency
Dividers
SCLK
SDATA
CPU_STOP#
PCI_STOP#
Vtt_PWRGD#
PD#
FS_A
FS_B
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
Power Groups
Pin Number
VDD
GND
36
24 25
10,16 11,17
36 39
55 54
34 33
N/A 53
48, 42
45
Description
Xtal, Ref
3V66 [0:3]
PCICLK outputs
SRCCLK outputs
Master clock, CPU Analog
48MHz, PLL, SCLK, SDATA
IREF
CPUCLK clocks
48MHz, USB, DOT, VCH
REF (1:0)
CPUCLKT (2:0)
CPUCLKC (2:0)
SRCCLKT0
SRCCLKC0
3V66(4:0)
PCICLK (6:0)
PCICLKF (2:0)
I REF
0701G—10/13/04
4



ICS952601 datasheet pdf
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