ICS952302 Datasheet PDF - Integrated Circuit Systems

www.Datasheet-PDF.com

ICS952302
Integrated Circuit Systems

Part Number ICS952302
Description Frequency Generator for TransmetaTM
Page 15 Pages


ICS952302 datasheet pdf
Download PDF
ICS952302 pdf
View PDF for Mobile


No Preview Available !

Integrated
Circuit
Systems, Inc.
ICS9523 0 2
Frequency Generator for TransmetaTM EfficeonTM
Recommended Application:
Transmeta Efficion, ATi M6
Output Features:
• 3 - CPUs @ 3.3V including 1 free running
CPUCLK_F
• 7 - PCI @ 3.3V, including 4 free running PCICLK_F
• 1 - 27MHz clock @ 3.3V
• 2 - 48MHz clocks @ 3.3V
• 2 - REF clocks @3.3V
Features:
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz referience input or XTAL.
• Full Load Power consumption reduced >10%
compared to reference device
• Power management via SMBus
Key Specifications:
• CPU output jitter: < 250ps
• PCI output skew: < 250ps
• CPUT - PCI output skew: 1-3ns
• 27MHz Accuracy < 50ppm
• 48MHz Accuracy < 50ppm
Functionality
Byte 4b7
0
0
0
0
1
1
1
1
Byte 4b6
0
0
1
1
0
0
1
1
Byte 4b5
0
1
0
1
0
1
0
1
Spread
%
+/-0.3
+/-0.6
+/-0.25
+/-0.45
CENTER
-0.60%
-1.20% DOWN
-0.50%
-0.90%
Pin Configuration
VDDREF 1
REF0 2
GNDREF 3
X1 4
X2 5
VDDPCI 6
PCICLK_F0 7
PCICLK_F1 8
GNDPCI 9
PCICLK0 10
PCICLK1 11
PCICLK_F2 12
PCICLK_F3 13
VDDPCI 14
PCICLK2 15
GNDPCI 16
N/C 17
N/C 18
VDDCOR 19
PCI_STOP# 20
**PD# 21
GND48 22
SDATA 23
SCLK 24
48-TSSOP
* Internal Pull-Up Resistor
**No Diode Clamp to VDD
48 REF1
47 VDDCPU
46 N/C
45 CPUCLK0
44 GNDCPU
43 CPUCLK1
42 CPUCLK_F
41 CPU_STOP#
40 GND
39 N/C
38 OE*
37 N/C
36 VDD
35 N/C
34 VDD27
33 GND
32 27MHZ
31 N/C
30 N/C
29 N/C
28 GND48
27 VDD48
26 48MHZ_1
25 48MHZ_0
0957B—10/05/04



No Preview Available !

ICS952302
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIN NAME
VDDREF
REF0
GNDREF
X1
X2
VDDPCI
PCICLK_F0
PCICLK_F1
GNDPCI
PCICLK0
PCICLK1
PCICLK_F2
PCICLK_F3
VDDPCI
PCICLK2
GNDPCI
N/C
N/C
VDDCOR
PCI_STOP#
21 **PD#
22 GND48
23 SDATA
24 SCLK
25 48MHZ_0
26 48MHZ_1
27 VDD48
28 GND48
29 N/C
30 N/C
31 N/C
32 27MHZ
33 GND
34 VDD27
35 N/C
36 VDD
37 N/C
38 OE*
39 N/C
40 GND
41 CPU_STOP#
42 CPUCLK_F
43 CPUCLK1
44 GNDCPU
45 CPUCLK0
46 N/C
47 VDDCPU
48 REF1
* Internal Pull-Up Resistor
PIN
TYPE
PWR
OUT
PWR
IN
OUT
PWR
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
OUT
PWR
N/C
N/C
PWR
IN
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
Ground pin for the REF outputs.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Ground pin for the PCI outputs
PCI clock output.
PCI clock output.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
Ground pin for the PCI outputs
No Connection.
No Connection.
3.3V power for the PLL core.
Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input.
IN Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used to power down the device. The
internal clocks are disabled and the VCO and the crystal are stopped.
PWR Ground pin for the 48MHz outputs
I/O Data pin for SMBus circuitry, 5V tolerant.
IN Clock pin of SMBus circuitry, 5V tolerant.
OUT 48MHz clock output.
OUT 48MHz clock output.
PWR Power pin for the 48MHz output.3.3V
PWR Ground pin for the 48MHz outputs
N/C No Connection.
N/C No Connection.
N/C No Connection.
OUT 27.0000MHz Video Clock for ATi Chipset
PWR Ground pin.
PWR Power pin for the 27MHz output.3.3V
N/C No Connection.
PWR Power supply, nominal 3.3V
N/C No Connection.
IN Active high input for enabling Memory Channel outputs.
0 = tri-state outputs, 1= enable outputs
N/C No Connection.
PWR Ground pin.
IN Stops all CPUCLK, except those set to be free running clocks
OUT Free running CPU clock. Not affected by the CPU_STOP#.
OUT CPU clock outputs. 3.3V
PWR Ground pin for the CPU outputs
OUT CPU clock outputs. 3.3V
N/C No Connection.
PWR Supply for CPU clocks, 3.3V nominal
OUT 14.318 MHz reference clock.
** No diode clamp to VDD.
0957B—10/05/04
2



No Preview Available !

ICS9523 0 2
General Description
Spread spectrum may be enabled through SMBus programming. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS952302 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process
and temperature variations.
Block Diagram
(1:0)
1 27MHz
(1:0)
1
(1:0)
PD#
OE
(2:0)
(3:0)
4
0957B—10/05/04
3



No Preview Available !

ICS952302
SMBus Table: Output Control Register
Byte 0
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
42
45
43
32
25
26
2
48
CPUCLK_F
CPUCLK0
CPUCLK1
27MHZ
48MHZ_0
48MHZ_1
REF0
REF1
Control
Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
SMBus Table: Output Control Register
Byte 1
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7 PCICLK_F0
8 PCICLK_F1
12 PCICLK_F2
13 PCICLK_F3
10 PCICLK0
11 PCICLK1
15 PCICLK2
- Spread Spectrum
Mode
Control
Function
Test Mode
Output Enable
Output Enable
Output Enable
Spread Control
Output Enable
Output Enable
Spread Control for PLL1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
OFF
SMBus Table: Output Control Register
Byte 2
Pin #
Name
Control
Function
Type
0
Bit 7
Bit 6
Bit 5
42
45
43
CPUCLK_F
CPUCLK0
CPUCLK1
Allow assertion of
RW Free Running
CPU_STOP# or setting of
CPU_STOP control bit in RW Free Running
SMBus register to stop
CPU clocks
RW Free Running
Bit 4
-
Reserved
Reserved
RW -
Bit 3
-
Reserved
Reserved
RW -
Bit 2
(note)
CPU_STOP
Stop all CPU clocks
RW
Enable
Bit 1
-
Reserved
Reserved
RW -
Bit 0
20, 41
CPU_STOP#
PCI_STOP#
H/w or S/w Select
RW
H/W
Note: Byte2bit2=0 (Enable) to stop all CPUCLK's ONLY when Byte2 bit(5:7) at STOPPABLE MODE
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
ON
1
Stoppable
Stoppable
Stoppable
-
-
Disable
-
I2C
SMBus Table: Output Control Register
Byte 3
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0957B—10/05/04
7
8
12
13
10
11
15
-
PCICLK_F0
PCICLK_F1
PCICLK_F2
PCICLK_F3
PCICLK0
PCICLK1
PCICLK2
PCI_STOP
Control
Function
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop PCI
clocks
Stop all PCI clocks
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Free Running
Free Running
Free Running
Free Running
Free Running
Free Running
Free Running
Enable
1
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
Disable
PWD
1
1
1
1
1
1
1
1
PWD
1
1
1
1
1
1
1
0
PWD
0
1
1
x
x
1
x
1
PWD
0
0
0
0
1
1
1
1
4



ICS952302 datasheet pdf
Download PDF
ICS952302 pdf
View PDF for Mobile


Related : Start with ICS95230 Part Numbers by
ICS952301 Frequency Timing Generator for Transmeta Systems ICS952301
Integrated Circuit Systems
ICS952301 pdf
ICS952302 Frequency Generator for TransmetaTM ICS952302
Integrated Circuit Systems
ICS952302 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact