ICS952301 Datasheet PDF - Integrated Circuit Systems

www.Datasheet-PDF.com

ICS952301
Integrated Circuit Systems

Part Number ICS952301
Description Frequency Timing Generator for Transmeta Systems
Page 12 Pages


ICS952301 datasheet pdf
Download PDF
ICS952301 pdf
View PDF for Mobile


No Preview Available !

Integrated
Circuit
Systems, Inc.
ICS952301
Advance Information
Frequency Timing Generator for Transmeta Systems
Recommended Application:
Transmeta
Output Features:
• 1CPU up to 66.6MHz &
overclocking of 66MHz.
• 7 PCI (3.3V) @ 33.3MHz (all are free running
selectable) w/ 2 selectable 1X/2X.
• 1 REF (3.3V) at 14.318MHz.
• 1 48MHz (3.3V).
• 1 24_48MHz selectable output.
Features:
• Supports Spread Spectrum modulation for CPU and
PCI clocks, default -2.0% downspread.
• Efficient Power management scheme through stop
clocks and power down modes.
• Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
• 28-pin TSSOP package, 4.40mm (173mil).
Skew Characteristics:
• PCI – PCI < 500ps
• CPU(early) – PCI = 1.5ns – 4ns.
Pin Configuration
GNDREF 1
X1 2
X2 3
PD# 4
PCICLK0 5
PCICLK1 6
GNDPCI 7
VDDPCI 8
PCICLK21 9
PCICLK3 10
PCICLK41 11
GNDPCI 12
VDDPCI 13
PCICLK5 14
28 VDDREF
27 REF/ 1X or 2X Programmable*
26 CPU_STOP#
25 VDDCPU/CORE
24 GNDCPU/CORE
23 CPUCLK0
22 PCI_STOP#
21 SCLK
20 VDD48
19 GND48
18 48MHz
17 24-48MHz/Sel 48_24#*
16 SDATA
15 PCICLK6
28-Pin 173mil TSSOP
Note: ^ Internal Pulldown Resistor
* Internal Pullup Resistor
1 1X/2X Programmable
Block Diagram
X1
XTAL
X2 OSC
REF
SCLOCK
SDATA
PD#
PCI_STOP#
SEL48_24#
CPU_STOP#
CPU
PLL
Control
Logic
PCI DIV
STOP
STOP
CPU
PCI(6:0)
48MHz
Power GroupsPLL
STOP
48MHz
VDD_Core, GND_Core = PLL core
24/48 STOP
24/48MHz
VDDREF, GNDREF = REF, X1, X2
VDDPCI, GNDPCI = PCICLK (6:0)
VDD48, GND48 = 48MHz (1:0)
0673—07/09/02
Pentium is a trademark on Intel Corporation.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.



No Preview Available !

ICS952301
Advance Information
Pin Descriptions
PIN # PIN
1 GNDREF
2 X1
3 X2
4 PD#
5 PCICLK0
6 PCICLK1
7 GNDPCI
8 VDDPCI
9 PCICLK21
10 PCICLK3
11 PCICLK41
12 GNDPCI
13 VDDPCI
14 PCICLK5
15 PCICLK6
16 SDATA
17
24-48MHz/Sel
48_24#*
18 48MHz
19 GND48
20 VDD48
21 SCLK
22 PCI_STOP#
23 CPUCLK0
24 GNDCPU/CORE
25 VDDCPU/CORE
26 CPU_STOP#
REF/ 1X or 2X
27 Programmable*
28 VDDREF
PIN
TYPE
PWR
IN
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
I/O
DESCRIPTION
Ground pin.
Crystal input, nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Asynchronous active low input pin used to power down the
device into a low power state. The internal clocks are
disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
PCI clock outputs.
PCI clock outputs.
Ground pin.
Supply for PCI, nominal 3.3V.
PCI clock outputs.
PCI clock outputs.
PCI clock outputs.
Ground pin.
Supply for PCI, nominal 3.3V.
PCI clock outputs.
PCI clock outputs.
Data pin for I2C circuitry 5V tolerant
I/O Selectable 48 or 24MHz output
OUT
PWR
PWR
IN
IN
OUT
PWR
PWR
IN
OUT
PWR
48MHz output clock
Ground pin.
Power for 24 & 48MHz output buffers and fixed PLL core.
Clock pin of I2C circuitry 5V tolerant
Stops all PCICLKs besides the PCICLK_F clocks at logic 0
level, when input low
CPU clock outputs.
Ground pin.
3.3V power for the PLL core.
Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0
level, when input low
14.318 MHz reference clock. Latched input select for strength
of PCICLK(4,2). Default 1X with internal pullup.
3.3V power for the REF.
0673—07/09/02
2



No Preview Available !

ICS952301
Advance Information
ICS952301 Power Management Requirements
CPU
PCI Byte 0 VCO
PCICLK PCICLK 24
48 REF
PD# STOP# STOP# Bit 0
0XXX
STOP
CPUCLK
0
LOW
Not Free
Run
LOW
Free-Run
LOW
MHz
LOW
MHZ
LOW
LOW
1
0
1
0
RUN
STOP
RUN
RUN
RUN
RUN
RUN
1
1
0
0
RUN
RUN STOP RUN
RUN
RUN
RUN
1 1 1 1 RUN Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State
Note: If Byte 3 bit [7:2]=0 Not Free-Run, can be controlled by PCI_STOP#
If Byte 3 bit [7:2]=1 Free-Run, cannot controlled by PCI_STOP#
0673—07/09/02
3



No Preview Available !

ICS952301
Advance Information
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Stop Bit
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
ICS (Slave/Receiver)
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
0673—07/09/02
4



ICS952301 datasheet pdf
Download PDF
ICS952301 pdf
View PDF for Mobile


Related : Start with ICS95230 Part Numbers by
ICS952301 Frequency Timing Generator for Transmeta Systems ICS952301
Integrated Circuit Systems
ICS952301 pdf
ICS952302 Frequency Generator for TransmetaTM ICS952302
Integrated Circuit Systems
ICS952302 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact