ICS952001 Datasheet PDF - Integrated Circuit Systems

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ICS952001
Integrated Circuit Systems

Part Number ICS952001
Description Preliminary Product Previes
Page 17 Pages


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Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
Programmable Timing Control Hub™ for P4™ processor
Recommended Application:
SIS 645/650 style chipsets.
Output Features:
• 2 - Pairs of differential CPUCLKs (differential current mode)
• 1 - SDRAM @ 3.3V
• 8 - PCI @3.3V
• 2 - AGP @ 3.3V
• 2 - ZCLKs @ 3.3V
• 1- 48MHz, @3.3V fixed.
• 1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
• 3- REF @3.3V, 14.318MHz.
Features/Benefits:
• Programmable output frequency, divider ratios, output
rise/falltime, output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• For PC133 SDRAM system use the ICS9179-06 as the
memory buffer.
• For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
• Uses external 14.318MHz crystal.
Key Specifications:
• PCI - PCI output skew: < 500ps
• CPU - SDRAM output skew: < 1ns
• AGP - AGP output skew: <150ps
Functionality
B it 2 B it 7 B it 6 B it 5 B it 4 C P U S D R A M Z C LK
FS4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(M H z )
66.67
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
80.00
80.00
95.00
95.00
66.67
(M H z )
66.67
100.00
200.00
133.33
150.00
125.00
160.00
133.33
200.00
166.67
166.67
133.33
133.33
95.00
126.67
66.67
(M H z )
66.67
66.67
66.67
66.67
60.00
62.50
66.67
80.00
66.67
62.50
71.43
66.67
66.67
63.33
63.33
50.00
AGP
(M H z )
66.67
66.67
66.67
66.67
60.00
62.50
66.67
66.67
66.67
62.50
83.33
66.67
66.67
63.33
63.33
50.00
Note: For additional margin testing frequencies, refer to Byte 4
952001 Rev A 01/24/02
Pin Configuration
VDDREF
**FS0/REF0
**FS1/REF1
**FS2/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
*PCI_STOP#
VDDPCI
**FS3/PCICLK_F0
**FS4/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDSD
47 SDRAM
46 GNDSD
45 CPU_STOP#*
44 CPUCLKT_1
43 CPUCLKC_1
42 VDDCPU
41 GNDCPU
40 CPUCLKT_0
39 CPUCLKC_0
38 IREF
37 GNDA
36 VDDA
35 SCLK
34 SDATA
33 PD#*/Vtt_PWRGD
32 GNDAGP
31 AGPCLK0
30 AGPCLK1
29 VDDAGP
28 VDDA48
27 48MHz
26 24_48MHz/MULTISEL*
25 GND48
48-Pin 300-mil SSOP and TSSOP
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
Block Diagram
PLL2
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
/2
CPU
DIVDER
Stop
48MHz
24_48MHz
REF (1:0)
2
2 CPUCLKT (1:0)
2 CPUCLKC (1:0)
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
MULTISEL
PD#/Vtt_PWRGD
Control
Logic
Config.
Reg.
ZCLK
DIVDER
PCI
DIVDER
Stop
AGP
DIVDER
ZCLK (1:0)
2
6 PCICLK (9:0)
PCICLK_F (1:0)
2
AGP (1:0)
2
I REF
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
VDDZ = ZCLK



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Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
General Description
The ICS952001 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero
delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks
signals for such a system.
The ICS952001 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
1, 11, 13, 19, 29,
42, 48
2
3
4
5, 8, 18, 24, 25,
32, 37, 41, 46
6
7
10, 9
PIN NAME
VDD
FS0
REF0
FS1
REF1
FS2
REF2
GND
X1
X2
ZCLK(1:0)
12 PCI_STOP#
14
15
23, 22, 21, 20, 17,
16
26
27
28, 36
30, 31
FS3
PCICLK_F0
FS4
PCICLK_F1
PCICLK (5:0)
MULTISEL
24_48MHz
48MHz
AVDD
AGPCLK (1:0)
PD#
33
Vtt_PWRGD
34 SDATA
35 SCLK
38 I REF
43, 39
44, 40
45
47
CPUCLKC (1:0)
CPUCLKT (1:0)
CPU_STOP#
SDRAM
TYPE
PWR
IN
OUT
IN
OUT
IN
OUT
PWR
IN
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
OUT
IN
IN
I/O
IN
OUT
OUT
OUT
IN
OUT
DESCRIPTION
Power supply for 3.3V
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Ground pin for 3V outputs.
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Hyperzip clock outputs.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
MODE pin is in Mobile mode
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
PCI clock outputs.
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
Clock output for super I/O/USB default is 24MHz
48MHz output clock
Analog power supply 3.3V
AGP outputs defined as 2X PCI. These may not be stopped.
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 3ms.
This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal.
When Vtt_PWRGD goes high the frequency select will be latched at
power on thereafter the pin is an asynchronous active low power down
pin.
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
This pin establishes the reference current for the CPUCLK
pairs. This pin requires a fixed precision resistor tied to ground
in order to establish the appropriate current.
"Complementary" clocks of differential pair CPU outputs. These clocks
are 180° out of phase with SDRAM clocks. These open drain outputs
need an external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These clocks are in phase
with SDRAM clocks. These open drain outputs need an external 1.5V pull-
up.
Stops all CPUCLKs clocks at logic 0 level, when MODE pin is in Mobile
mode
SDRAM clock output.
Third party brands and names are the property of their respective owners.
2



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Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
CPUCLK Swing Select Functions
MULTSEL0
0
0
0
0
1
1
1
1
Byte 23
Bit 7
0
0
1
1
0
0
1
1
Board Target
Trace/Term Z
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
Reference R,
Iref=
Vdd/(3*Rr)
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Output
Current
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0
0
30 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 5*Iref
0
0
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 5*Iref
0
1
30 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 4*Iref
0
1
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 4*Iref
1
0
30 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 6*Iref
1
0
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 6*Iref
1
1
30 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 7*Iref
1
1
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Ioh = 7*Iref
Voh @ Z,
Iref=2.32mA
0.71V @ 60
0.59V @ 50
0.56V @ 60
0.47V @ 50
0.85V /2 60
0.71V @ 50
0.99V @ 60
0.82V @ 50
0.75V @ 30
0.62V @ 20
0.60 @ 20
0.5V @ 20
0.90V @ 30
0.75V @ 20
1.05V @ 30
0.84V @ 20
Third party brands and names are the property of their respective owners.
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Integrated
Circuit
Systems, Inc.
ICS952001
Preliminary Product Preview
General I2C serial interface information for the ICS952001
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
*See notes on the following page.
Third party brands and names are the property of their respective owners.
4
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D2(H)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address D3(H)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P stoP bit
Byte N + X - 1



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