ICS843S104I-133 Datasheet PDF - IDT

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ICS843S104I-133
IDT

Part Number ICS843S104I-133
Description Crystal-to-LVPECL 133MHz Clock Synthesizer
Page 24 Pages


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Crystal-to-LVPECL 133MHz
Clock Synthesizer
ICS843S104I-133
DATA SHEET
General Description
The ICS843S104I-133 is a PLL-based clock
ICS synthesizer specifically designed for low phase noise
HiPerClockS™ applications. This device generates a 133.33MHz
differential LVPECL clock from an input reference of
25MHz. The input reference may be derived from an
external source or by the addition of a 25MHz crystal to the on-chip
crystal oscillator. An external reference is applied to the PCLK,
nPCLK pins.The device offers spread spectrum clock output for
reduced EMI applications. An I2C bus interface is used to enable or
disable spread spectrum operation as well as to select either a down
spread value of -0.35% or -0.5%.The ICS843S104I-133 is available
in a lead-free 32-Lead VFQFN package.
Features
Four LVPECL output pairs
Crystal oscillator interface: 25MHz
Differential PCLK/nPCLK input pair
PCLK/nPCLK supports the following input types: LVPECL, CML,
SSTL
Output frequency: 133.33MHz
PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant
RMS phase jitter @ 133.33MHz (12kHz – 20MHz):
1.2ps (typical)
I2C support with readback capabilities up to 400kHz
Spread Spectrum for electromagnetic interference (EMI) reduction
3.3V operating supply mode
-40°C to 85°C ambient operating temperature
Available lead-free (RoHS 6) package
Block Diagram
REF_SEL Pulldown
PCLK Pulldown
nPCLK Pullup/Pulldown
25MHz
XTAL_IN
OSC
XTAL_OUT
SDATA Pullup
SCLK Pullup
1
PLL
0
I2C
Logic
4
Q[1:4]
4
nQ[1:4]
Pin Assignment
32 31 30 29 28 27 26 25
VCC 1
24 VEE
REF_SEL 2
23 nQ3
VEE 3
22 Q3
PCLK 4
21 VCC
nPCLK 5
20 VEE
VEE 6
19 nQ4
VCCA 7
18 Q4
VEE 8
17 VCC
9 10 11 12 13 14 15 16
ICS843S104I-133
32-Lead VFQFN
5.0mm x 5.0mm x 0.925mm
package body
K Package
Top View
ICS843S104BKI-133 REVISION A JUNE 9, 2009
1
©2009 Integrated Device Technology, Inc.



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ICS843S104I-133 Data Sheet
CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 17, 21, 25,
28, 29
2
3, 6, 8, 9,
10, 20, 24, 32
4
Name
VCC
REF_SEL
VEE
PCLK
5 nPCLK
7 VCCA
11 VCC_XOSC
12, XTAL_IN,
13 XTAL_OUT
14 nc
15 SCLK
16
18,19
22, 23
26, 27
30, 31
SDATA
Q4, nQ4
Q3, nQ3
Q2, nQ2
Q1, nQ1
Type
Description
Power
Core supply pins.
Input
Pulldown
Select input for XTAL (LOW) or REF_IN (HIGH).
LVCMOS/LVTTL interface levels.
Power
Negative power supply pins.
Input
Input
Power
Power
Pulldown
Pullup/
Pulldown
Non-inverting external 25MHz differential reference input.
LVPECL input levels.
Inverting external 25MHz differential reference input. LVPECL input levels.
Analog supply for PLL.
Analog supply for crystal oscillator.
Input
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Unused
Input
I/O
Output
Output
Output
Output
Pullup
Pullup
No connect.
I2C compatible SCLK. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
I2C compatible SDATA. This pin has an internal pullup resistor.
LVCMOS/LVTTL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol Parameter
CIN Input Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
ICS843S104BKI-133 REVISION A JUNE 9, 2009
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©2009 Integrated Device Technology, Inc.



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ICS843S104I-133 Data Sheet
CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal I2C serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock output
buffers, can be individually enabled or disabled. The registers
associated with the serial interface initialize to their default settings
upon power-up, and therefore, use of this interface is optional. Clock
device register changes are normally made upon system
initialization, if any are required.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block
write and block read operations from the controller. For block
write/read operations, the bytes must be accessed in sequential
order from lowest to highest byte (most significant bit first) with the
ability to stop after any complete byte has been transferred. For byte
write and byte read operations, the system controller can access
individually indexed bytes. The offset of the indexed byte is encoded
in the command code, as described in Table 3A.
The block write and block read protocol is outlined in Table 3B, while
Table 3C outlines the corresponding byte write and byte read
protocol. The slave receiver address is 11010010 (D2h).
Table 3A.Command Code Definition
Bit 7
Description
0 = Block read or block write operation,
1 = Byte read or byte write operation.
6, 5
Chip select address, set to
“00” to access device.
4:0
Byte offset for byte read or byte write
operation. For block read or block write
operations, these bits must be “00000”.
ICS843S104BKI-133 REVISION A JUNE 9, 2009
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©2009 Integrated Device Technology, Inc.



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ICS843S104I-133 Data Sheet
CRYSTAL-TO-LVPECL 133MHZ CLOCK SYNTHESIZER
Table 3B. Block Read and Block Write Protocol
Bit Description = Block Write
1 Start
2:8 Slave address - 7 bits
9 Write
10 Acknowledge from slave
11:18
Command Code - 8 bits
19 Acknowledge from slave
20:27
Byte Count - 8 bits
28 Acknowledge from slave
29:36
Data byte 1 - 8 bits
37 Acknowledge from slave
38:45
Data byte 2 - 8 bits
46 Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N - 8 bits
Acknowledge from slave
Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
Description = Block Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave - 8 bits
Acknowledge
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from Slave/Acknowledge
Data Byte N from slave - 8 bits
Not Acknowledge
Stop
Table 3C. Byte Read and Byte Write Protocol
Bit Description = Byte Write
1 Start
2:8 Slave address - 7 bits
9 Write
10 Acknowledge from slave
11:18
Command Code - 8 bits
19 Acknowledge from slave
20:27
Data byte - 8 bits
28 Acknowledge from slave
29 Stop
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39
Description = Byte Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read
Acknowledge from slave
Data from slave - 8 bits
Not Acknowledge
Stop
ICS843S104BKI-133 REVISION A JUNE 9, 2009
4
©2009 Integrated Device Technology, Inc.



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