IC89E54 Datasheet PDF - Integrated Circuit Solution


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IC89E54
Integrated Circuit Solution

Part Number IC89E54
Description (IC89E54 / IC89E64) 8-BITS SINGLE MICROCONTROLLER
Page 30 Pages

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IC89E54/58/64
8-BITS SINGLE MICROCONTROLLER
with 16/32/64-Kbytes of FLASH,
256 byte +512 byte RAM
FEATURES
• 80C52 based architecture
• 256 Byte RAM internal RAM and 512 Bytes
auxiliary RAM available
• Three 16-bit Timer/Counters
• Full duplex serial channel
• Boolean processor
• Power Save Mode :
1) Idle Mode
2) Power Down Mode - waken up from interrupt
level trigger mode
• Program memory lock
– Lock bits (3)
• Four 8-bit I/O ports, 32 I/O lines
• Memory addressing capability
– 64K Program Memory and 64K Data Memory
• CMOS and TTL compatible
• Maximum speed ranges at Vcc = 5V is 40 MHz
and most instructions execute in 0.3 µs
• Packages available:
– 40-pin DIP
– 44-pin PLCC
– 44-pin PQFP
• 16K/32K/64K Byte Flash Memory with fast-pulse
programming algorithm
36 I/O pins(above 44-pin package only)
8 interrupts vectors (above 44-pin package
only)
Low EMI mode
GENERAL DESCRIPTION
IC89E54, IC89E58, IC89E64 are members of ICSI
embedded microcontroller family. The IC89E54/58/64 uses
the same powerful instruction set, has the same architecture,
and is pin-to-pin compatible with standard 80C51 controller
devices. They have IC89E54/58/64 all functions and some
enhanced function is included. These enhanced functions
include 512 bytes auxiliary memory, 36 I/O pins (44 pin
package only), 8 interrupts (44 pin package only) with two-
level priority, Power off flag, Low EMI mode, power down
mode is waken up from interrupt level trigger mode.
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA/VPP
30 ALE/PROG
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
Figure 1. IC89E54/58/64 Pin Configuration: 40-pin DIP
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated C ircuitSolution Inc.
MC012-0C 11/16/2001
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IC89E54/58/64
INDEX
6 5 4 3 2 1 44 43 42 41 40
P1.5 7
39 P0.4/AD4
P1.6 8
38 P0.5/AD5
P1.7 9
37 P0.6/AD6
RST 10
36 P0.7/AD7
RxD/P3.0 11
INT2/P4.3 12
TOP VIEW
35 EA/VPP
34 P4.1
TxD/P3.1 13
33 ALE/PROG
INT0/P3.2 14
32 PSEN
INT1/P3.3 15
31 P2.7/A15
T0/P3.4 16
30 P2.6/A14
T1/P3.5 17
29 P2.5/A13
18 19 20 21 22 23 24 25 26 27 28
Figure 2. IC89E54/58/64 Pin Configuration: 44-pin PLCC
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IC89E54/58/64
P1.5
P1.6
P1.7
RST
RxD/P3.0
INT2/P4.3
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
P4.1
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
Figure 3. IC89E54/58/64 Pin Configuration: 44-pin PQFP/LQFP
Integrated C ircuitSolution Inc.
MC012-0C 11/16/2001
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IC89E54/58/64
VCC
VSS
P2[7:0]
P0[7:0]
16K/32K/64K
MAIN CODE
FLASH
SFR
BLOCK
256
BYTE
RAM
512
BYTE
AUX
RAM
80C32 CPU CORE
CLOCK
&
TIMING
INT 2
INT 3
ALE
PSEN
RST
EA
XTAL2
XTAL1
PORT 4
P4[3:0]
PORT 1
TIMER 2
UART
INT0
INT1
TIMER 0 TIMER 1
PORT 3
P1[7:0]
P3[7:0]
Figure 4. IC89E54/58/64 Block Diagram
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MC012-0C 11/16/2001




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