IA6805E2 Datasheet PDF - InnovASIC

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IA6805E2
InnovASIC

Part Number IA6805E2
Description Microprocessor Unit
Page 30 Pages


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IA6805E2
Microprocessor Unit
Preliminary Data Sheet
FEATURES
Form, Fit, and Function Compatible with the Harris© CDP6805E2CE and Motorola©
MC146805E2
Internal 8-bit Timer with 7-Bit Programmable
Prescaler
On-chip Clock
Memory Mapped I/O
Versatile Interrupt Handling
True Bit Manipulation
Bit Test and Branch Instruction
Vectored Interrupts
Power-saving STOP and WAIT Modes
Fully Static Operation
112 Bytes of RAM
The IA6805E2 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces
replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This
technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible
with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon
technology advances. MILESTM also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA6805E2 including functional and I/O descriptions, electrical characteristics, and applicable
timing.
Functional Block Diagram
RESET_N
IRQ_N
LI
DS
RW_N
AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
A12
A11
A10
A9
A8
VSS
(1) IA6805E2
(2)
40 Pin DIP
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
(21)
VDD
OSC1
OSC2
TIMER
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
B0
B1
B2
B3
B4
B5
B6
B7
AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
NC
NC
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
IA6805E2
44 Pin LCC
(39) PB1
(38) PB2
(37) PB3
(36) PB4
(35) PB5
(34) PB6
(33) PB7
(32) B0
(31) B1
(30) B2
(29) B3
Copyright © 2000
innovASIC
The End of Obsolescence
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IA6805E2
Preliminary Data Sheet
Microprocessor Unit
Figure 1 illustrates the IA6805E2. The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low
cost, low power MPU. It features a CPU, on-chip RAM, parallel I/O compatibility with pins
programmable as input or output. The following paragraphs will further describe this system block
diagram and design in more detail.
Figure 1: System Block Diagram
TIMER
PRESCALER
TIMER/
COUNTER
TIMER CONTROL
OSC1 OSC2
OSCILLATOR
PA0
PORT
A
I/O
LINES
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PORT
A
REG
DATA
DIR
REG
PORT
B
I/O
LINES
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PORT
B
REG
DATA
DIR
REG
ACCUMULATOR
8A
INDEX
REGISTER
8X
CONDITION
CODE
5 REGISTER CC
STACK
POINTER
6 SP
PROGRAM
COUNTER
5 HIGH PCH
PROGRAM
COUNTER
8 LOW PCL
CPU
RESET_N
LI
IRQ_N
CPU
CONTROL
ALU
112x8
RAM
MUX
BUS
DRIVE
B0
B1
B2 MULTIPLEXED
B3 ADDRESS
B4 DATA
BUS
B5
B6
B7
ADDRESS
DRIVE
A8
A9
A10
ADDRESS
BUS
A11
A12
BUS
CONTROL
AS
DS
RW_N
ADDRESS STROBE
DATA STROBE
READ/WRITE
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IA6805E2
Microprocessor Unit
Preliminary Data Sheet
Functional Overview
I/O Signal Description
The table below describes the I/O characteristics for each signal on the IC. The signal names correspond to
the signal names on the pinout diagrams provided.
SIG N A L N A M E
V DD and V SS
(Power and Ground)
RESET_n
(R e s e t )
IR Q _ n
(Interrupt Request)
LI
(Load Instruction)
DS
(D a ta Strobe)
RW_n
(R e a d / W rite)
AS
(Address Strobe)
PA0-PA7/PB0-PB7
(Input/Output Lines)
A8-A12
(H igh Order Address Lines)
B0-B7
(Address/Data Bus)
T im e r
OSC1, OSC2
(System C lock)
C rystal
External Clock
I/O
N/A
I
I
O
O
O
O
I/O
O
I/O
I
I/O
DESCRIPTION
S o u r c e : T h e s e t w o pins provide p o w e r to the chip. V D D provides + 5 volts (±0.5) p o w e r
a n d V SS is ground.
T T L : I n p u t pin t h a t c a n b e u s e d to r e s e t t h e M P U 's i n t e r n a l state b y p u l l i n g t h e r e s e t _ n
pin low.
T T L : I n p u t pin t h a t is level a n d e d g e s e n s i t i v e . C a n b e u s e d to r e q u e s t a n i n t e r r u p t
sequence.
T T L w ith s l e w rate c o n t r o l : O u t p u t pin u s e d to i n d i c a t e t h a t a n e x t o p c o d e fetch is in
p r o g r e s s . U s e d o n l y f o r certain d e b u g g i n g a n d test s y s t e m s . N o t c o n n e c t e d in n o r m a l
o p e r a t i o n . O v e r l a p s D ata S t r o b e ( D S ) signal. T h i s o u t p u t is c a p a b l e o f driving o n e
standard TTL load and 50pF.
T T L w ith slew rate c o n t r o l : O u t p u t pin u s e d to transfer data to o r from a peripheral o r
m e m o r y . D S occurs anytim e t h e M P U d o e s a data read o r w rite a n d during data transfer
to o r f r o m i n t e r n a l m e m o r y . D S is available a t f O S C ÷ 5 w h e n t h e M P U is n o t in t h e W A I T
or STOP mode. This output is capable of driving one standard TTL load and 130pF.
T T L w ith slew rate c o n t r o l : O u t p u t pin used to indicate t h e direction o f d a t a transfer
from internal memory, I/O registers, and external peripheral devices and memories.
I n d i c a t e s to a s e l e c t e d p e r i p h e r a l w h e t h e r t h e M P U is to r e a d (R W _ n h i g h ) o r w r i t e
(R W _ n l o w ) d a t a o n t h e n e x t d a t a s t r o b e . T h i s o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d
TTL load and 130pF.
T T L w ith slew rate control: O u t p u t strobe used to indicate the presence o f an address
o n t h e 8-bit m u l t i p l e x e d b u s . T h e A S line is u s e d to d e m u l t i p l e x t h e e i g h t least s i g n i f i c a n t
a d d r e s s b i t s f r o m t h e d a t a b u s . A S is available a t fO S C ÷ 5 w h e n t h e M P U is n o t in t h e
W A I T o r S T O P m o d e s . T h i s o u t p u t is c a p a b l e o f driving o n e s t a n d a r d T T L l o a d a n d
130pF.
T T L w ith slew rate c o n t r o l : T h e s e 16 lines constitute I n p u t / O u t p u t p o r t s A a n d B .
E a c h line is i n d i v i d u a l l y p r o g r a m m e d to b e e i t h e r an i n p u t o r o u t p u t u n d e r s o f t w a r e
c o n t r o l o f t h e D ata D irection R e g i s t e r ( D D R ) as s h o w n b e l o w in T a b l e 1 a n d F i g u r e 2 .
T h e p o r t I / O is p r o g r a m m e d b y w r i t i n g t h e c o r r e s p o n d i n g b i t in t h e D D R to a " 1 " f o r
output and a "0" for input. In the output m o d e the bits are latched and appear on the
c o r r e s p o n d i n g o u t p u t p i n s . A ll t h e D D R 's are i n i t i a l i z e d to a " 0 " o n r e s e t . T h e o u t p u t
p o r t registers are n o t initialized on reset. E a c h o u t p u t is c a p a b l e o f driving o n e s t a n d a r d
TTL load and 50pF.
T T L w ith slew rate control: T h e s e five o u t p u t s constitute t h e h i g h e r o r d e r n o n -
m u l t i p l e x e d a d d r e s s l i n e s . E a c h o u t p u t is c a p a b l e o f driving o n e s t a n d a r d T T L l o a d a n d
130pF.
T T L w ith slew rate control: T h e s e bi-directional lines constitute the l o w e r o r d e r
addresses a n d data. T h e s e lines are m ultiplexed w ith a d d r e s s present at address strobe
tim e a n d d a t a p r e s e n t a t d a t a s t r o b e tim e. W h e n in t h e d a t a m o d e , t h e s e lines are bi-
directional, transferring data to a n d from m e m o r y a n d peripheral d e v i c e s as indicated b y
the R W _ n pin. A s outputs, these lines are capable o f driving o n e standard T T L load and
130pF.
T T L : Input used to control the internal tim er/counter circuitry.
T T L O scillator input/output: These pins provide control input for the on-chip clock
oscillator circuits. E ither a crystal o r external c l o c k is c o n n e c t e d to these p i n s to p r o v i d e
a s y s t e m c l o c k . T h e crystal c o n n e c t i o n is s h o w n in F i g u r e 3 . T h e O S C 1 to b u s
transitions for system designs using oscillators slower than 5M H z is shown in Figure 4.
T h e circuit s h o w n in F i g u r e 3 is r e c o m m e n d e d w h e n using a c r y s t a l . A n e x t e r n a l C M O S
o s c i l l a t o r is r e c o m m e n d e d w h e n using crystals o u t s i d e t h e s p e c i f i e d r a n g e s . T o m inim ize
output distortion and start-up stabilization tim e , the crystal and components should be
mounted as close to the input pins as possible.
W h e n an e x t e r n a l clock is u s e d , it s h o u l d b e a p p l i e d to t h e O S C 1 i n p u t w ith t h e O S C 2
input not connected, as shown in Figure 3.
Copyright © 2000
innovASIC
The End of Obsolescence
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IA6805E2
Microprocessor Unit
Preliminary Data Sheet
Table 1
I/O Pin Functions
R/W-n DDR
I/O Pin Functions
0 0 The I/O pin is in iput mode. Data is written
into the output data latch.
0 1 Data is written into the output data latch and
output to the I/O pin.
1 0 The state of the I/O pin is read.
1 1 the I/O pin is in an output mode. The
output data latch is read.
Figure 2: PA0-PA7/PB0-PB7 (Input/Output Lines)
I/O Port Circutry and Register Configuration:
DATA DIRECTION
REGISTER
BIT
TO
AND LATCHED
OUTPUT
FROM DATA BIT
CPU INPUT
REG
BIT
OUTPUT
I/O
PIN
INPUT
I/O
PIN
76543210
DATA DIRECTION
A(B)
REGISTER
DDA7
(DDB7)
DDA6
(DDB6)
DDA5
(DDB5)
DDA4
(DDB4)
DDA3
(DDB3)
DDA2
(DDB2)
DDA1
(DDB1)
DDA0
(DDB0)
$0004 ($0005)
PORT A(B)
REGISTER
$0000 ($0001)
Copyright © 2000
innovASIC
The End of Obsolescence
PIN
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
(PB7) (PB6) (PB5) (PB4) (PB3) (PB2) (PB1) (PB0)
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