IA4432 Datasheet PDF - Integration

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IA4432
Integration

Part Number IA4432
Description ISM Transceiver
Page 30 Pages


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IA4432 ISM Transceiver
DESCRIPTION
Integration’s I A4432 transceiver is a member of the new EZRa dioPROTM fa mily.
While re taining all the a ttractive fe atures o f earli er pr oducts such as h igh
integration, low cost, flexibility, low Bill of Materials (BOM) cost, and easy design-in,
these par ts ar e targe ted t o m ore so phisticated appl ications an d offe r sev eral
enhanced para meters and fea tures, inc luding contin uous fre quency cov erage
from 240- 930MHz and output power up to +20dBm. Also inc luded are built- in
features like an tenna d iversity algorithm, wak e-up ti mer, low b attery d etector,
temperature se nsor, gen eral purpose Anal og t o Dig ital Conv erter (A DC), TX/R X
First-In First-Out Buffers (FIFO’s), power-on-reset (POR), and general purpose I/Os
(GPIOs). The chip incorporates a high performance ADC in the RX path and digital
modem which performs demodulation, filtering, and packet handling in the digital
domain making it ideal for configuration to multiple applications. These features
simplify the task of th e sys tem designer a nd allow for t he use o f lowe r-end
Microcontrollers. A highly efficient +20dBm po wer amplifier (P A) is completely
integrated which eliminates the need for a n external PA and mak es the part ideal
for Fre quency Hopp ing Sy stems where maximu m range is desire d. The devices
comply with FCC and ETSI req uirements wh en u sed in any of the standard IS M
bands. On ly a 30MHz crysta l and a limi ted number of pa ssive matching/filtering
components ar e necessar y as e xternal com ponents mak ing the device id eal fo r
high volume production in applications where size and cost are critical.
The IA4432 is a CMOS Radio Frequency Integrated circuit which incorporates all of
the transmit and receive functions required for ISM band applications. The chip is
designed to operate over a w ide range of frequencies, voltages, and temperature
with ex tremely l ow curren t cons umption which makes it ideal for low-data rate
battery powered applications.
FUNCTIONAL BLOCK DIAGRAM
VDD_RF
RF LDO
TX
PA
VCO LDO
VCO
ANTDIV
TXRXSW
PA_RAMP
PWR_CTRL
AGC Control
RFp
RFn
VR_IF
LNA
IF LDO
Mixers
BIAS
PGA
PLL LDO
LPF CP
RC 32K OSC
PFD
30M XTAL
OSC
N
LBD
Temp
Sensor
8Bit
ADC
Delta Sigma
Modulator
TXMOD Digital Logic
SPI, & Controller
SCLK
SDI
SDO
VDD_DIG
GND_DIG
Digital Modem
ADC
Low Power
Digital LDO
Digital LDO
POR
IA4432
QFN-20 PIN ASSIGNMENT
VDD_RF
TX
RXp
RXn
VR_IF
Metal
Paddle
20 19 18 17 16
1 15
2 14
3 13
4 12
5 11
6 7 8 9 10
SCLK
SDI
SDO
VDD_DIG
GND_DIG
See back page for ordering information.
FEATURES
Frequency Range = 240-
930MHz
Sensitivity =-117dBm
+20dBm Max Output
Power
o Configurable +11 to
+20dBm
Low Power Consumption
o 17mA Receive
o 60mA Transmit
@+20dBm
o 27mA@+13dBm
Data Rate = 1 to
128kbps
Power Supply = 1.8 to
3.6V
Ultra Low Power
Shutdown Mode
Digital RSSI
Wake-On-Radio
Auto-Frequency
Calibration (AFC)
Antenna Diversity & TR
Switch Control
Configurable Packet
Structure
Preamble Detector
TX & RX 64 byte FIFOs
Low Battery Detector
Temperature Sensor
and 8bit ADC
-40°C - +85°C
Temperature Range
Integrated Voltage
Regulators
Frequency Hopping
Capability
On-chip Crystal Tuning
20-Pin QFN Package
FSK, GFSK, and OOK
Modulation
Low BOM
Power-on-Reset(POR)
TYPICAL APPLICATIONS
Remote Control
Remote Meter Reading
Home Security & Alarm Remote Keyless Entry
Telemetry
Home Automation
Personal Data Logging Industrial Control
Toy Control
Sensor Networks
Tire Pressure Monitoring Health Monitors
Wireless PC Peripherals Tag Readers
IA4432-DS rev 0.9r 0508
PRELIMINARY
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IA4432
TABLE OF CONTENTS
1 Detailed Description .....................................................................................................................................................6
2 Functional Description .................................................................................................................................................7
2.1 Pin Connection Diagram ......................................................................................................... ..................................................... 8
2.2 Package Pin Definitions ........................................................................................................ ....................................................... 9
2.3 Operating Modes ................................................................................................................ ........................................................ 10
3 Electrical Specifications............................................................................................................................................ 11
3.1 Definition of Test Conditions.................................................................................................. .................................................... 15
3.2 Absolute Maximum Ratings ....................................................................................................... ................................................ 17
4 Controller Interface.................................................................................................................................................... 18
4.1 Serial Peripheral Interface (SPI) .............................................................................................. .................................................. 18
4.2 Operating Mode Control ......................................................................................................... .................................................... 20
4.2.1 Shutdown State................................................................................................................. ..................................................... 21
4.2.2 Idle State ..................................................................................................................... ........................................................... 21
4.2.3 TX State ....................................................................................................................... ........................................................... 21
4.2.4 RX State....................................................................................................................... ........................................................... 22
4.2.5 Device Status .................................................................................................................. ....................................................... 22
4.2.6 Interrupts..................................................................................................................... ........................................................... 23
4.2.7 Device Code .................................................................................................................... ....................................................... 25
4.2.8 System Timing.................................................................................................................. ...................................................... 25
4.2.9 Frequency Control.............................................................................................................. .................................................... 28
4.2.10 TX Data Rate Generator ......................................................................................................... ............................................... 32
5 Modulation Options.................................................................................................................................................... 33
5.1 Modulation Type ................................................................................................................ ......................................................... 33
5.2 Modulation Data Source ......................................................................................................... ................................................... 33
5.3 FIFO Mode...................................................................................................................... ............................................................. 34
5.4 Direct Mode .................................................................................................................... ............................................................ 34
5.5 PN9 Mode ....................................................................................................................... ............................................................ 34
5.6 Synchronous vs. Asynchronous ................................................................................................... .............................................. 34
6 Internal Functional Blocks ........................................................................................................................................ 37
6.1 RX LNA ......................................................................................................................... ............................................................... 37
6.2 RX I-Q Mixer ................................................................................................................... ............................................................. 37
6.3 Programmable Gain Amplifier.................................................................................................... ................................................ 37
6.4 ADC............................................................................................................................ .................................................................. 37
6.5 Digital Modem .................................................................................................................. .......................................................... 37
6.6 Synthesizer .................................................................................................................... ............................................................. 38
6.6.1 VCO ............................................................................................................................ ............................................................. 38
6.7 Power Amplifier................................................................................................................ ........................................................... 39
6.7.1 Output Power Selection ......................................................................................................... ................................................ 39
6.8 Crystal Oscillator............................................................................................................. ............................................................ 39
6.9 Regulators..................................................................................................................... .............................................................. 40
7 Data Handling and Packet Handler .......................................................................................................................... 41
7.1 RX and TX FIFOs ................................................................................................................ ......................................................... 41
7.2 Packet Configuration........................................................................................................... ....................................................... 42
7.3 Packet Handler TX Mode......................................................................................................... ................................................... 42
7.4 Packet Handler RX Mode ......................................................................................................... .................................................. 43
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IA4432
7.4.1 Packet Handler Disabled .......................................................................................................................................................43
7.4.2 Packet Handler Enabled........................................................................................................................................................43
7.5 Packet Handler Registers and Descriptions .............................................................................................................................44
7.6 Data Whitening, Manchester Encoding, and CRC.....................................................................................................................51
7.7 Preamble Detector .....................................................................................................................................................................51
7.8 Preamble Length ........................................................................................................................................................................51
7.9 Invalid Preamble Detector .........................................................................................................................................................52
7.10 TX Retransmission and Auto TX.................................................................................................................................................52
8 RX Modem configuration........................................................................................................................................... 53
8.1 Channel Filter BW.......................................................................................................................................................................53
9 Auxiliary Functions..................................................................................................................................................... 53
9.1 POR .............................................................................................................................................................................................53
9.2 Microcontroller Clock .................................................................................................................................................................54
9.3 General Purpose ADC.................................................................................................................................................................55
9.3.1 ADC Differential Input Mode – Bridge Sensor Example ......................................................................................................57
9.4 Temperature Sensor ............................................................................................................. ..................................................... 58
9.5 Low Battery Detector........................................................................................................... ....................................................... 59
9.6 Wake-Up Timer .................................................................................................................. ......................................................... 60
9.7 Low Duty Cycle Mode ............................................................................................................ ..................................................... 61
9.8 GPIO Configuration ............................................................................................................. ........................................................ 61
9.9 Antenna-Diversity .............................................................................................................. ......................................................... 65
9.10 TX/RX Switch Control ........................................................................................................... ...................................................... 65
9.11 RSSI and Clear Channel Assessment.............................................................................................. .......................................... 65
9.12 Analog and Digital Test Bus .................................................................................................... ................................................... 66
10 Package Information ............................................................................................................................................. 70
10.1 Dimensions ..................................................................................................................... ............................................................ 70
11 Reference Design................................................................................................................................................... 71
12 Measurement Results ........................................................................................................................................... 76
13 Application Notes................................................................................................................................................... 82
13.1 Crystal Selection.............................................................................................................. ........................................................... 82
13.2 Layout Practice ................................................................................................................ ........................................................... 82
13.3 Matching Network Design........................................................................................................ .................................................. 82
13.3.1 RX LNA Matching ................................................................................................................ ................................................... 82
13.3.2 TX PA Matching and Filtering ................................................................................................... ............................................. 83
13.4 Microcontroller Connection..................................................................................................... ................................................... 84
14 Reference Material ................................................................................................................................................ 85
14.1 Complete Register Table and Descriptions...............................................................................................................................85
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IA4432
LIST OF FIGURES
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+20dBm Application with Antenna Diversity and FHSS ................................................................................................... 7
IA4432 Pinout .................................................................................................................. .................................................. 8
Production Test Schematic...................................................................................................... ........................................ 16
SPI Timing..................................................................................................................... .................................................... 18
SPI Timing –READ Mode.......................................................................................................... ........................................ 19
SPI Timing –Burst Write Mode ................................................................................................... ..................................... 19
SPI Timing –Burst Read Mode.................................................................................................... ..................................... 19
State Machine Diagram .......................................................................................................... ......................................... 20
TX Timing ...................................................................................................................... .................................................... 27
RX Timing...................................................................................................................... .................................................... 27
FSK vs. GFSK Spectrum.......................................................................................................... ......................................... 33
Direct Synchronous Mode Example ................................................................................................ ................................ 35
Direct Asynchronous Mode Example............................................................................................... ................................ 35
FIFO Mode Example .............................................................................................................. ........................................... 36
PLL Synthesizer Block Diagram.................................................................................................. ..................................... 38
FIFO Thresholds ................................................................................................................ ............................................... 41
Packet Structure ............................................................................................................... ............................................... 42
Multiple Packets in TX Packet Handler .......................................................................................... ................................. 42
Required RX Packet Structure with Packet Handler Disabled ...................................................................... .................43
Multiple Packets in RX Packet Handler.......................................................................................... ................................. 43
Multiple Packets in RX with CRC or Header Error................................................................................ ........................... 43
Operation of Data Whitening, Manchester Encoding, and CRC...................................................................... ...............51
POR Glitch Parameters .......................................................................................................... .......................................... 54
General Purpose ADC Architecture ............................................................................................... .................................. 56
ADC Differential Input Example – Bridge Sensor ................................................................................. .......................... 57
Temperature Ranges using ADC8 .................................................................................................. ................................. 59
Low Duty Cycle Mode ............................................................................................................ ........................................... 61
GPIO Usage Examples............................................................................................................ .......................................... 64
RSSI Value vs. Input Frequency................................................................................................. ...................................... 66
Package Dimensions ............................................................................................................. .......................................... 70
Reference Design Schematic ..................................................................................................... ..................................... 71
Reference Design Layout........................................................................................................ ......................................... 73
Antenna Diversity Reference Design Schematic ................................................................................... ......................... 74
Antenna Diversity Reference Design Layout...................................................................................... ............................. 75
Sensitivity vs. Data Rate ...................................................................................................... ............................................ 76
Receiver Selectivity ........................................................................................................... ............................................... 77
TX Output Power vs. VDD voltage ................................................................................................ .................................... 78
TX Output Power vs Temperature................................................................................................. ................................... 78
TX Modulation (40kbps, 20khz Deviation) ........................................................................................ ............................. 79
TX Unmodulated Spectumr (917MHz) ............................................................................................... ............................. 79
TX Modulated Spectrum (917MHz, 40kbps, 20kHz Deviation, GFSK) ................................................................. .......80
Synthesizer Settling Time for 1MHz Jump settled within 10kHz ................................................................... ................80
Synthesizer Phase Noise (VCOCURR=’11’)......................................................................................... ............................ 81
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