IA2004-CE40A Datasheet PDF - Rohm

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IA2004-CE40A
Rohm

Part Number IA2004-CE40A
Description Image sensor heads
Page 5 Pages


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IA2004-CE40A
Image sensor heads for narrow-width scanners
IA2004-CE40A
The IA 04-ME/CE series sensors, compatible with A6 size media, feature a dual-arch structure, allowing straight pass
reading (both-directions). In addition, they are compact, measuring only 119.5mm in length.
zApplications
Check readers, card scanners, and a variety of other image input devices.
zFeatures
1) Signal amplifier integrated into each sensor IC in order to eliminate external noise ; compatible with 3.3V interface.
2) LED light source mounted on the same substrate as the sensor chip itself, resulting in a more compact, lightweight
package.
3) Proprietary prism maintains a uniform output signal.
4) Ceramic substrate used, ensuring excellent dimensional and thermal stability.
zDimensions (Unit : mm)
119.5±0.3
109.6 (Effectiv Reading Width :104.6)
CL
No.1 Pixel
3.96±0.5
60±0.3
A
29.75±0.3
5±0.1
φ2±0.05
(Depth 1)
10.7±0.4
15.5±1
25±1
(NOTE 1)
Deflection at the top of glass:0-0.25
Projection to platen is positive.
(NOTE 2)
Socket Housing:IL-Z-9S-S125C3(JAE)
Socket Contact:IL-Z-C3-A-15000(JAE)
No.9
(12.9)
(3.8)
No.1
Pin No.
No.1
No.2
No.3
No.4
No.5
No.6
Signal
CLK
SP
VDD
GND
AO
RLED
Pin No.
No.7
No.8
No.9
Signal
GLED
BLED
VLED
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zCharacteristics
Parameter
Effective scanning width
Primary scan dot density
Total dot number
Power supply voltage
Scanning speed
Clock frequency
Maximum dynamic range
Minimum dynamic range
Dark output
Operating temperature
Symbol
VDD
SLT
CLK
VRMax.
VRMin.
Vod
Typ.
104.6
200
864
5
0.125×3
8
0.5
0.25
1.2±0.4
5 to 45
Unit
mm
dpi
dots
V
ms / line
MHz
V
V
V
°C
zPin assignments
No. Circuit
I/O
Functions
1 CLK
I Clock
2 SP
I Start Pulse
3 VDD
I Power Supply
4 GND
I Ground
5 Ao
O Analog Output
6 RLED
I LED ground
7 GLED
I LED ground
8 BLED
I LED ground
9 VLED
I LED power supply
IA2004-CE40A
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zTiming chart
(a) CLK Timing Chart
CLK
50%
50%
SP
tSETUP tHOLD
50%
IA2004-CE40A
twCLK
1/fCLK
twCLK
50%
50%
ts
Ao
1pixel
2pixel
(b) Data Output Timing Chart
After turning on the SP pulse, the analog output shape starts from the setting up point of 65 clock pulse.
CLK
SP
Ao
12
52 53 54
64 65 66
VREF Output Period (52pixels)
1 to 52 pixels
Vdummy
53 to 64pixels
Analog Output Period
1 to 864pixels
Note) Output blank part cannot be used as the analog output standard level.
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zEquivalent circuit
VDD
1µF x 2
GND
1
SP
CLK
ANALOG MEMORY CIRCUIT
Vout
VLED
1µF
RGND
GGND
BGND
zPeripheral circuit
IA2004-CE40A
864 200
1µF
VDD 75
VREF
87695
B GR
C3
LED GND
C4
VLED
A
3214
C2
R2
C1
R1
VDD SP CLK
GND
R1=R2=100
C1=47µF, C2=100pF
C3=100µF, C4=0.1µF
Please adjust the value of resistance to fit your interface circuit.
4/4



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