HY5RS123235FP-12 Datasheet PDF - Hynix Semiconductor

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HY5RS123235FP-12
Hynix Semiconductor

Part Number HY5RS123235FP-12
Description 512M (16Mx32) GDDR3 SDRAM
Page 30 Pages


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HY5RS123235FP
512M (16Mx32) GDDR3 SDRAM
HY5RS123235FP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.3 / Feb. 2006
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HY5RS123235FP
Revision History
Revision
No.
History
Draft Date
Remark
0.1 Defined target spec.
0.2 Page 11) Add Cas Latency 11
Page 14) Write Latency definitions
Page15) DI, WR_A, AL definitions
Page47) Table18 typo corrected
Page48) Table19 renewered
Page50) note 46 added
Mar. 2004
JULY.2004
CL
WL
DI/WR_A/AL
Speed BIN
Several Parameters
tRPRE
0.3 Page4) Ballout configurations correct
Appendix C) BST function description
0.4 - Non-Consectutive Read to Write timing clarifications
- Read to Precharge timing Clarifications
Aug.2004
A3/A8/A9/A10
Sep.24,2004
Page28
page41
Page23
0.5 - Modified the pin descriptions and added command description Nov.8,2004
for BST
- Added the LP mode feature for EMRS
Page4,6,21
Page15,16
0.6 -Added the Lead free package part number and Package dimen- Jan.31,2005
sion page
Page3,56
1.0 - Clarified the ODT control and Data terminator disable command Apr.30,2005
and its duration timing
- Modify the Data termination disable mode note of EMRS
- Modified the PIN description of VDDA/ VSSA(K1,12/J1,12)
- Changed the tPDIX, from 4tCK to 6tCK
- Changed the tXSRD, from 300tCk to 1000tCK
- Added the tCJC definition
- IDD spec update
- DC spec Update
1.1
VDD/VDDQ change, 500Mhz Speed Bin Insert, IDD value tuning
Jun. 2005
& typo corrected
1.2 VDD/VDDQ Change at 600MHz speed bin to 1.8V from 2.0V
Nov. 2005
1.3 900MHz speed bin insert
Feb. 2006
Page 15,20
Page 9
Page 4,7
Page 47
Page 48
page 48
page 46
Table 12
Rev. 1.3 / Feb. 2006
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HY5RS123235FP
DESCRIPTION
The Hynix HY5RS123235 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.
The Hynix HY5RS123235 is internally configured as a eight-bank DRAM.
The Hynix HY5RS123235 uses a double data rate architecture to achieve high-speed opreration. The double date rate architecture
is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the Hynix HY5RS123235 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM
core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the Hynix
HY5RS123235 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ of WRITE com-
mand. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed
(BA0,BA1, BA2 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command
are used to select the starting column location for the burst access. Prior to normal operation, the Hynix HY5RS123235 must be ini-
tialized.
FEATURES
• 2.2V +/-0.1V VDD/VDDQ power supply supports 900MHz
• 2.0V VDD/ VDDQ wide range min/max power supply
supports 700/ 800MHz
• 1.8V VDD/ VDDQ wide range min/max power supply
supports 500 / 600MHz
• Single ended READ Strobe (RDQS) per byte
• Single ended WRITE Strobe (WDQS) per byte
• Internal, pipelined double-data-rate (DDR) architecture;
two data accesses per clock cycle
• Calibrated output driver
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• RDQS edge-aligned with data for READ; with WDQS
center-aligned with data for WRITE
• Eight internal banks for concurrent operation
• Data mask (DM) for masking WRITE data
• 4n prefetch
• Programmable burst lengths: 4, 8
• 32ms, 8K-cycle auto refresh
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 1.8V Pseudo Open Drain I/O
• Concurrent Auto Precharge support
• tRAS lockout support, Active Termination support
• Programmable Write latency(1, 2, 3, 4, 5, 6)
• Boundary Scan Feature for connectivity test(refer to JEDEC
std., not in this version of Specifications)
- See Appendix B
ORDERING INFORMATION
Part No.
HY5RS123235FP-11
HY5RS123235FP-12
HY5RS123235FP-14
HY5RS123235FP-16
HY5RS123235FP-2
Power Supply
VDD=2.2V,
VDDQ=2.2V
VDD=2.0V,
VDDQ=2.0V
VDD=1.8V,
VDDQ=1.8V
Clock Frequency Max Data Rate
900MHz
800MHz
700MHz
600MHz
500MHz
1800Mbps/pin
1600Mbps/pin
1400Mbps/pin
1200Mbps/pin
1000Mbps/pin
Note) HY5RS123235FP-xx is the Lead Free Package part number
Interface
POD_18
Package
12mmx14mm
136Ball FBGA
Rev. 1.3 / Feb. 2006
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HY5RS123235FP
BALLOUT CONFIGURATION
12
3
4 5678 9
10
11 12
A VDDQ VDD VSS ZQ
MF VSS VDD VDDQ
B VSSQ DQ0 DQ1 VSSQ
VSSQ DQ9 DQ8 VSSQ
C VDDQ DQ2 DQ3 VDDQ
VDDQ DQ11 DQ10 VDDQ
D VSSQ WDQS0 RDQS0 VSSQ
VSSQ RDQS1 W DQS1 VSSQ
E VDDQ DQ4 DM0 VDDQ
VDDQ DM1 DQ12 VDDQ
F VDD DQ6 DQ5 CAS#
CS# DQ13 DQ14 VDD
G VSS VSSQ DQ7 BA0
BA1 DQ15 VSSQ VSS
H VREF A1 RAS# CKE
W E# BA2 A5 VREF
J VSS NC RFU VDDQ
VDDQ CK# CK VSS
K VDD A10 A2 A0
A4 A6 A8/AP VDD
L VSS VSSQ DQ25 A11
A7 DQ17 VSSQ VSS
M VDD DQ24 DQ27 A3
A9 DQ19 DQ16 VDD
N VDDQ DQ26 DM3 VDDQ
VDDQ DM2 DQ18 VDDQ
P VSSQ WDQS3 RDQS3 VSSQ
VSSQ RDQS2 W DQS2 VSSQ
R VDDQ DQ28 DQ29 VDDQ
VDDQ DQ21 DQ20 VDDQ
T VSSQ DQ30 DQ31 VSSQ
VSSQ DQ23 DQ22 VSSQ
U VDDQ VDD VSS SEN
RES VSS VDD VDDQ
Configuration
Refresh Count
Bank Address
Row Address
Column Address
AP Flag
Rev. 1.3 / Feb. 2006
16M x 32
2M x 32 x 8 banks
8k
BA0 - BA2
A0~A11
A0~A7, A9
A8
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