HI-8571 Datasheet PDF - HOLTIC

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HI-8571
HOLTIC

Part Number HI-8571
Description (HI-8570 / HI-8571) ARINC 429 LINE DRIVER
Page 8 Pages


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August 2006
HI-8570, HI-8571
+/- 5V Supply, ARINC 429 LINE DRIVER
DESCRIPTION
The HI-8570 and HI-8571 are CMOS integrated circuits
designed to directly drive the ARINC 429 bus in an 8-pin
package. Two logic inputs control a differential voltage
between the output pins producing a +10 volt One, a
-10 volt Zero, and a 0 volt Null.
A logic input is provided to control the slope of the
differential output signal. Timing is set by an on-chip
resistor and capacitor and tested to be within ARINC
requirements.
The HI-8570 has 37.5 ohms in series with each line driver
output. The HI-8571 provides the option to bypass part of
the output resistance so external resistance may be
added for lightning protection circuits.
The HI-8570 or the HI-8571 along with the HI-8588 line
receiver offer the smallest options available to get on and
off theARINC 429 bus.
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FEATURES
! Direct ARINC 429 line driver interface
in a small package
! On-chip line driver slope control and
selection by logic input
! Low current 5 volt supplies
! CMOS / TTL logic pins
! Plastic and ceramic package options -
surface mount and DIP
! Thermally enhanced SOIC packages
! Mil processing available
PIN CONFIGURATION
SLP1.5 1
TX0IN 2
TX1IN 3
GND 4
8 V+
7 TXBOUT
6 TXAOUT
5 V-
SUPPLY VOLTAGES
V+ = +5V
V- = -5V
FUNCTION TABLE
TX1IN TX0IN SLP1.5
00
X
01
0
01
1
10
0
10
1
11
X
TXAOUT
0V
-5V
-5V
5V
5V
0V
TXBOUT
0V
5V
5V
-5V
-5V
0V
SLOPE
N/A
10ms
1.5ms
10ms
1.5ms
N/A
PIN DESCRIPTION TABLE
PIN SYMBOL
1 SLP 1.5
2 TX0IN
3 TX1IN
4 GND
5 V-
6 TXAOUT
7 TXBOUT
8 V+
FUNCTION
LOGIC INPUT
LOGIC INPUT
LOGIC INPUT
POWER
POWER
OUTPUT
OUTPUT
POWER
DESCRIPTION
CMOS OR TTL, V+ IS OK
CMOS OR TTL
CMOS OR TTL
GROUND
-5 VOLTS
LINE DRIVER TERMINAL A
LINE DRIVER TERMINAL B
+5 VOLTS
(DS8570 Rev. B)
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HI-8570, HI-8571
FUNCTIONAL DESCRIPTION
Figure 1 is a block diagram of the line driver. The +5V and
-5V levels are generated from the supply voltages. Cur-
rents for slope control are set by zener voltages across on-
chip resistors.
The TX0IN and TX1IN inputs receive logic signals from a
control transmitter chip such as the HI-6010, HI-3282, HI-
8282A, HI-8584 or HI-8783. TXAOUT and TXBOUT hold
each side of the ARINC bus at Ground until one of the
inputs becomes a One. If for example TX1IN goes high, a
charging path is enabled to 5V on an “A” side internal
capacitor while the “B” side is enabled to -5V. The charg-
ing current is selected by the SLP1.5 pin. If the SLP1.5
pin is high, the capacitor is nominally charged from 10% to
90% in 1.5µs. If SLP1.5 is low, the rise and fall times are
10µs.
A unity gain buffer receives the internally generated slopes
and differentially drives the ARINC line. Current is limited
by the series output resistors at each pin. There are no
fuses at the outputs of the HI-8570 as exists on the HI-
8382.
The HI-8570 has 37.5 ohms in series with each output and
the HI-8571 has 27.5 ohms in series with each output.
The HI-8571 is for applications where external series re-
sistance is required, typically for lightning protection de-
vices.
Both the HI-8570 and HI-8571 are built using high-speed
CMOS technology. Care should be taken to ensure the
V+ and V- supplies are locally decoupled and that the
input waveforms are free from negative voltage spikes
which may upset the chip’s internal slope control circuitry.
TX0IN
TX1IN
ESD
PROTECTION
AND
VOLTAGE
TRANSLATION
ONE
NULL
ZERO
CONTROL
LOGIC
5V “A” SIDE
CURRENT
CONTROL
-5V
SLP1.5
HI-8570 = 37.5 OHMS
HI-8571 = 27.5 OHMS
TXAOUT
ONE
NULL
ZERO
CONTROL
LOGIC
5V “B” SIDE
CURRENT
CONTROL
-5V
HI-8570 = 37.5 OHMS
HI-8571 = 27.5 OHMS
FIGURE 1 - LINE DRIVER BLOCK DIAGRAM
TXBOUT
APPLICATION INFORMATION
Figure 2 shows a possible application
of the HI-8570/8571 interfacing an
ARINC transmit channel from the HI-
6010.
HARDWIRED
OR
{
DRIVEN FROM LOGIC
ARINC
Channel
ARINC
Channel
5V
1
2
VCC
TESTA
ROUTA
6
8
TESTB
7
ROUTB
4 HI-8588
RINA
3
RINB
5
5V
18
SLP1.5
6 TXAOUT
V+
TX1IN
7 HI-8570
TXBOUT
TX0IN
3
2
GND
4
V-
5
RXD1
RXD0
HI-6010
8 BIT BUS
TXD1
TXD0
-5V
FIGURE 2 - APPLICATION DIAGRAM
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HI-8570, HI-8571
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to Ground
Supply voltages
V+....................................................+7V
V-......................................................-7V
DC current per input pin................. +10mA
Power dissipation at 25°C
plastic DIL............1.0W, derate 10mW/°C
ceramic DIL..........0.5W, derate 7mW/°C
Solder Temperature ........275°C for 10 sec
Storage Temperature........-65°C to +150°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltages
V+....................................+4.8V to +5.3V
V-..................................... -5.3V to -4.8V
Temperature Range
Industrial Screening.........-40°C to +85°C
Hi-Temp Screening........-55°C to +125°C
Military Screening..........-55°C to +125°C
NOTE: Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to
the device. These are stress ratings only.
Operation at the limits is not recommended.
DC ELECTRICAL CHARACTERISTICS
V+ = +5V, V- = -5V, TA = Operating Temperature Range (unless otherwise stated)
PARAMETERS
SYMBOL TEST CONDITIONS
MIN TYP MAX UNITS
Input voltage (TX1IN, TX0IN, SLP1.5)
high
low
VIH
VIL
2.1 - V+ volts
- - 0.5 volts
Input current (TX1IN, TX0IN, SLP1.5)
source
IIH VIN = 0V
sink IIL VIN = 5V
- - 0.1 mA
- - 0.1 mA
ARINC output voltage (Differential)
one
zero
null
VDIFF1
VDIFF0
VDIFFN
no load; TXAOUT - TXBOUT 9.00 10.00 11.00
no load; TXAOUT - TXBOUT -11.00 -10.00 -9.00
no load; TXAOUT - TXBOUT -0.50 0 0.50
volts
volts
volts
ARINC output voltage (Ref. to GND)
one or zero
null
VDOUT no load & magnitude at pin
VNOUT no load
4.50 5.00 5.50
-0.25 0 0.25
volts
volts
Operating supply current
V+
V-
SLP1.5 = V+
IDD TX1IN & TX0IN = 0V: no load -
6.0 10.0 mA
IEE TX0IN & TX1IN = 0V: no load -10.0 -6.0 - mA
ARINC output impedence
HI-8570
HI-8571
ZOUT
- 37.5 - ohms
- 27.5 - ohms
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HI-8570, HI-8571
AC ELECTRICAL CHARACTERISTICS
V+ = 5.0V, V- = -5V, TA = Operating Temperature Range (unless otherwise stated)
PARAMETERS
SYMBOL TEST CONDITIONS
Line Driver propagation delay
Output high to low
Output low to high
Line Driver transition times
High Speed
Output high to low
Output low to high
Low Speed
Output high to low
Output low to high
t phlx
t plhx
defined in Figure 3, no load
SLP 1.5 = V+
t fx pin 1 = logic 1
t rx pin 1 = logic 1
SLP 1.5 = GND
t fx pin 1 = logic 1
t rx pin 1 = logic 1
Input capacitance (1)
logic
Notes:
1. Guaranteed but not tested
CIN
MIN TYP MAX UNITS
- 500 -
- 500 -
ns
ns
1.0 1.5 2.0
1.0 1.5 2.0
µs
µs
5.0 10.0 15.0
5.0 10.0 15.0
µs
µs
- - 10 pF
pin 3
t phlx
5V
0V
pin 2
t plhx
VDIFF
10%
pin 6 - pin 7
t plhx
t phlx
t rx
90%
t rx
90%
10%
10%
t fx
5V
0V
10V
0V
-10V
t fx
FIGURE 3 - LINE DRIVER TIMING
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