HI-8482 Datasheet PDF - Holt Integrated Circuits


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HI-8482
Holt Integrated Circuits

Part Number HI-8482
Description ARINC 429 DUAL LINE RECEIVER
Page 10 Pages

HI-8482 datasheet pdf
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February 2001
GENERAL DESCRIPTION
PIN CONFIGURATIONS (Top Views)
The HI-8482 bus interface unit is a silicon gate CMOS de-
vice designed as a dual differential line receiver in accor-
dance with the requirements of the ARINC 429 bus spec-
ification. The device translates incoming ARINC 429 sig-
nals to normal CMOS/TTL levels on each of its two inde-
pendent receive channels. The HI-8482 is also function-
ally equivalent to the Fairchild/Raytheon RM3183.
The self-test inputs force the outputs to either a ZERO,
ONE, or NULL state for system tests. While in self-test
mode, the ARINC inputs are ignored.
All the ARINC inputs have built-in hysteresis to reject
noise that may be present on the ARINC bus. Additional
input noise filtering can also be accomplished with exter-
nal capacitors.
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
The HI-8482 line receiver is one of several options of-
fered by Holt Integrated Circuits to interface to the ADRaINtaCSheet4U.com
bus. The digital data processing for serial-to-parallel con-
version and clock recovery can be accomplished with the
-VS - 1
HI-6010, HI-8683 or similar devices.
TESTA - 2
CAP2B - 3
The HI-8482 is available in a variety of ceramic & plastic
IN2B - 4
packages including Small Outline (SOIC), J-Lead PLCC,
Cerquad, DIP & Leadless Chip Carrier (LCC).
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
FEATURES
+VL - 9
N/C - 10
HI-8482J
HI-8482JT
20 - PIN
PLASTIC
J-LEAD PLCC
HI-8482PSI
HI-8482PST
20 - PIN
PLASTIC
SMALL
OUTLINE
(SOIC) - WB
18 - IN1A
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
DataShee
20 - TESTB
19 - CAP1A
18 - IN1A
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
13 - N/C
12 - OUT1B
11 - +VS
! Converts ARINC 429 levels to digital data
! Direct replacement for the RM3183
! Greater than 2 volt receiving hysteresis
! TTL and CMOS outputs and test inputs
! Military screening available
! 20-Pin SOIC, PLCC, CERQUAD. DIP &
LCC packages are available
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ARINC INPUTS
V (A) - V (B)
Null
Zero
One
Don't Care
Don't Care
Don't Care
TRUTH TABLE
TEST INPUTS
TEST A TEST B
00
00
00
01
10
11
OUTPUTS
OUT A OUT B
00
01
10
01
10
00
(DS8482 Rev. C)
DaStheet 4 Ucom.
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HI-8482
FUNCTIONAL DESCRIPTION
The HI-8482 contains two independent ARINC 429 receive
channels. The diagram in Figure 1 illustrates a typical HI-
8482 receive channel.
The differential ARINC signal input is converted to a positive
signal referenced to ground through level shifters and a
unity gain differential amplifier.
A positive differential input signal is converted to a positive
signal on the plus output of the differential amplifier. This
output is proportional in amplitude to the original input
signal. At the same time, the corresponding MINUS output
is pulled to GND. Likewise when a negative input signal is
present at the ARINC inputs, a positive signal is present on
the MINUS output and the PLUS output is pulled to GND.
ARINC LEVELS
The ARINC 429 specification requires the following
detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5V to +13V
+2.5V to -2.5V
-6.5V to -13V
The HI-8482 guarantees recognition of these levels with a
common mode voltage with respect to GND less than
±5V for the worst case condition.
NOISE
The outputs of the differential amplifier are compared with
the ONE, ZERO and NULL threshold levels to produce the
appropriate logic level on the OUTA and OUTB outputs of
the device. The ARINC clock signal may be recovered
through a NOR function of OUTA and OUTB.
The input hysteresis is set to reject voltage level transitions
in the undefined region between the maximum ZERO level
and the minimum NULL level and the undefined region
between the maximum NULL level and the minimum ONE
level. Therefore, once a valid input differential voltage
threshold is detected, the outputs will remain at a valid logic
The test inputs logically disconnect the outputs of the state until a new valid input voltage is detected.
comparators from OUTA and OUTB and force the device
et4U.comoutputs to one of the three valid states (Figure 5). This
alleviates having to ground the ARINC inputs during test
In addition to the
it possible to add
hsyimstpelreeRsiCs,ftihlteerCs atoptAheanAdRCINaCpBinppiuntssm. akeDataShee
mode operation.
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TESTA
TESTB
INA
CAPA
INB
CAPB
DataSheet4U.com
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LEVEL
SHIFT
LEVEL
SHIFT
Detect
Level
Comp
DIFF Comparators
AMP w / hysteresis
Detect
Level
Comp
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HI-8482
TYPICAL APPLICATIONS
APPLICATIONS
The standard connections for the HI-8482 are shown in Figure 2.
Decoupling of the supply should be done near the IC to avoid
propagation of noise spikes due to switching transients. The
ground (GND) connection should be sturdy and isolated from large
switching currents to provide a quiet ground reference.
The HI-8482 can be used with HI-8382 or HI-8585 Line Drivers to
provide a complete analog ARINC 429 interface solution. A simple
application, which can be used in systems requiring a repeater
type circuit for long transmissions or for test interfaces, is given in
Figure 3. More HI-8382 or HI-8585 drivers may be added to test
multiple ARINC channels, as shown.
ARINC RECEIVER STANDARD CONNECTIONS
+5V +15V
ARINC
CHANNEL 1
ARINC
CHANNEL 2
et4U.com
LOGIC
TEST
INPUTS
HI-8482
IN1A
OUT1A
39 pF
39 pF
IN1B
CAP1A
CAP1B
OUT1B
39 pF
39 pF
IN2A
IN2B
CAP2A
CAP2B
OUT2A
OUT2B
DataSTEhSeTeAt4U.com
TESTB
N/C
N/C
A CHANNEL 1
DATA OUT
B TO LOGIC
A CHANNEL 2
DATA OUT
B TO LOGIC
DataShee
-15V
ARINC
INPUT
CHANNEL
IN1A
IN1B
ARINC REPEATER CIRCUIT
OUT1A
OUT1B
DATA (A)
DATA (B)
AOUT
BOUT
DATA (A)
DATA (B)
AOUT
BOUT
A ARINC
OUTPUT
B CHANNEL 1
A ARINC
OUTPUT
B CHANNEL 2
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HI-8482
PIN DESCRIPTION TABLE
SYMBOL FUNCTION
DESCRIPTION
CAP1A
INPUT Filter capacitor input for terminal A of
channel 1
CAP1B
INPUT Filter capacitor input for terminal B of
channel 1
CAP2A
INPUT Filter capacitor input for terminal A of
channel 2
CAP2B
INPUT Filter capacitor input for terminal B of
channel 2
GND POWER 0 Volts
IN1A
INPUT ARINC input terminal A of channel 1
IN1B
INPUT ARINC input terminal B of channel 1
IN2A
INPUT ARINC input terminal A of channel 2
SYMBOL FUNCTION
DESCRIPTION
IN2B
INPUT ARINC input terminal B of channel 2
OUT1A OUTPUT TTL output terminal A of channel 1
OUT1B OUTPUT TTL output terminal B of channel 1
OUT2A OUTPUT TTL output terminal A of channel 2
OUT2B OUTPUT TTL output terminal B of channel 2
TESTA INPUT Test input terminal A
TESTB INPUT Test input terminal B
+VL POWER +5 Volts ±10%
+Vs POWER +12 Volts ±10% or +15 Volts ±10%
-Vs POWER -12 Volts ±10% or -15 Volts ±10%
TIMING DIAGRAMS
et4U.com
+10V
ARINC
DIFFERENTIAL 0V
INPUT
-10V
OUTA
OUTB
TESTA
TESTB
+5V
0V
+5V
0V
OUTA (test)
OUTB (test)
DataSheet4U.com
aSDhetat 4 Uomc.
DataSheet4U.com
tPLH
50%
tPHL
tPLH
FIGURE 4.
tPHL
50%
tTLH
50%
tTHL
tTLH
tTHL
50%
FIGURE 5.
HOLT INTEGRATED CIRCUITS
4
tr tf
90%
10%
DataShee
tr tf
90%
10%




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