HI-8456 Datasheet PDF - HOLTIC

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HI-8456
HOLTIC

Part Number HI-8456
Description Octal ARINC 429 Line Receivers
Page 16 Pages


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December 2016
HI-8456, HI-8457, HI-8458
Octal ARINC 429 Line Receivers with
Integrated DO-160G Level 3 Lightning Protection
GENERAL DESCRIPTION
Holt’s family of octal ARINC 429 line receivers, HI-8456,
HI-8457 and HI-8458 include internal lightning protection
circuitry which ensures compliance with RTCA/DO-
160G, Section 22 Level 3 Pin Injection Test Waveform
Set A (3 & 4), Set B (3 & 5A) and Set Z (3 & 5B) without
the use of any external components. Each device
contains 8 independent ARINC 429 line receivers. Pin
surge levels for Level 3 are summarized below.
Waveform
3
VOC/ISC
600V/24A
Waveform
4
VOC/ISC
300V/60A
Waveform
5A
VOC/ISC
300V/300A
Waveform
5B
VOC/ISC
300V/300A
The devices are designed to operate from either a 5V or
3.3V supply in a high noise environment, with an input
common mode voltage range of ±30V. Each receiver
channel translates incoming ARINC 429 data bus
signals to a pair of TTL / CMOS outputs.
FEATURES
Internal lightning protection circuitry ensures
compliance with RTCA/DO-160G, Section 22
Level 3 Pin Injection Test Waveform Set A (3 &
4), Set B (3 & 5A) and Set Z (3 & 5B)
Direct connection to ARINC 429 bus with no
external components
High input common mode voltage range of ±30V
Non-annunciated fault protection; a receiver will
reject a signal when either bus line is open or
shorted to ground.
3.3V or 5.0V single supply operation
Test inputs bypass analog inputs and force digital
outputs to a one, zero, or null state (not available
on HI-8457)
Industrial and Extended temperature ranges
Burn-in available
In the case of HI-8456 and HI-8458, the TESTA and
TESTB inputs bypass the analog inputs for testing
purposes. They force the outputs of all eight receivers
to the specified ZERO, ONE or NULL state. The ARINC
inputs are ignored when the devices are in test mode.
The HI-8456 has a single test port which controls
all 8 channels simultaneously. The HI-8458 has two
independent test ports, each controlling a bank of 4
channels. Test inputs are not implemented on HI-8457
and are internally connected to logic 0. The truth table
for the TESTA and TESTB inputs is shown in Table 1.
The HI-8456 and HI-8457 are exact drop in replacements
for DEI1046 and DEI1047 respectively. The HI-8458 is
pin-to-pin compatible with Holt’s HI-8448 and is also a
drop-in replacement for the DEI1148 (44-pin PQFP). A
part number cross reference is included in Table 2.
The parts are available in Industrial -40oC to +85oC, or
Extended, -55oC to +125oC temperature ranges. Optional
burn-in is available on the extended temperature range.
PIN CONFIGURATION (TOP VIEW)
IN1A 1
IN1B 2
IN2A 3
IN2B 4
IN3A 5
IN3B 6
IN4A 7
IN4B 8
IN5A 9
IN5B 10
IN6A 11
IN6B 12
IN7A 13
IN7B 14
IN8A 15
IN8B 16
NC 17
* TESTA 18
* TESTB 19
HI-8456PS
HI-8457PS
Octal
Receiver
38 OUT1A
37 OUT1B
36 OUT2A
35 OUT2B
34 OUT3A
33 OUT3B
32 OUT4A
31 OUT4B
30 VSS
29 VDD
28 VSS
27 OUT5A
26 OUT5B
25 OUT6A
24 OUT6B
23 OUT7A
22 OUT7B
21 OUT8A
20 OUT8B
38 Pin Plastic TSSOP Package
* No Connect on HI-8457
DS8458 Rev. C
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HI-8456, HI-8457, HI-8458
ARINC
INPUTS
INA - INB
-2.5 to +2.5V
< -6.5V
> +6.5V
x
x
x
Note (1): Not available on HI-8457.
Table 1.  Function Table
TESTA(1)
TESTB(1)
OUTA
000
000
001
010
101
110
OUTB
0
1
0
1
0
0
FUNCTIONAL DESCRIPTION
Figure 1 shows the general architecture of an ARINC 429 receiver. The receiver operates off the VDD supply only. The
inputs INA and INB may be connected directly to the ARINC 429 bus. Internal lightning protection circuitry ensures
compliance with RTCA/DO-160G, Section 22 Level 3 Pin Injection Test Waveform Set A (3 & 4), Set B (3 & 5A) and
Set Z (3 & 5B) without the use of any external components.
After level translation, the inputs are buffered and become inputs to a differential amplifier. The amplitude of the
differential signal is compared to levels derived from a divider between VDD and Ground. The nominal settings
correspond to a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V.
The status of the ARINC receiver input is latched. A Null input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal which is generated by the logical OR of the TESTA and TESTB
pins (not available on HI-8457). If TESTA and TESTB are both One, the outputs are pulled low. This allows the digital
outputs of a transmitter to be connected to the test inputs through control logic for system self-test purposes.
NON-ANNUNCIATED FAULT PROTECTION
A fault condition may cause one side of the ARINC 429 bus transmission line to become open or shorted to ground.
When this condition occurs, it is desirable that the receiver rejects the incoming signal. The receiver thresholds are
set above 5.5V (the maximum signal level under this one-wire fault condition), so that signals associated with this
non-annunciated fault condition are rejected. This fault protection will also ensure that voltage levels undefined by the
ARINC 429 Specification (the voltage range between ±2.5V and ±6.5V) are also rejected.
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BLOCK DIAGRAMS
INA
INB
LIGHTNING
PROTECTION
AND
TRANSLATION
HI-8456, HI-8457, HI-8458
ONE
NULL
ZERO
NULL
SQ
LATCH
R
TEST
TESTA
TESTB
SQ
LATCH
R
TEST
TESTA
TESTB
Figure 1.  Line Receiver Block Diagram
ROUTA
ROUTB
IN1A
IN1B
IN3A
IN3B
IN5A
IN5B
IN7A
IN7B
TESTAA
TESTAB
TESTBA
TESTBB
IN2A
IN2B
IN4A
IN4B
IN6A
IN6B
IN8A
IN8B
HI-8458
OUT1A
OUT1B
OUT3A
OUT3B
OUT5A
OUT5B
OUT7A
OUT7B
OUT2A
OUT2B
OUT4A
OUT4B
OUT6A
OUT6B
OUT8A
OUT8B
IN1A
IN1B
IN3A
IN3B
IN5A
IN5B
IN7A
IN7B
OUT1A
OUT1B
OUT3A
OUT3B
OUT5A
OUT5B
OUT7A
OUT7B
TESTA
TESTB
(Test inputs not
connected on HI-8457)
IN2A
IN2B
IN4A
IN4B
IN6A
IN6B
IN8A
IN8B
OUT2A
OUT2B
OUT4A
OUT4B
OUT6A
OUT6B
OUT8A
OUT8B
HI-8456 / HI-8457
Figure 2.  Block Diagrams.
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DEI
Part Number
DEI1046-TES-G
DEI1046-TMS-G
DEI1047-TES-G
DEI1047-TMS-G
DEI1148-QES-G
DEI1148-QMS-G
HI-8456, HI-8457, HI-8458
Table 2.  Cross Reference Table
Holt
Part Number
HI-8456PSTF
HI-8456PSTF
HI-8457PSTF
HI-8457PSTF
HI-8458PQTF
HI-8458PQTF
Package
38-pin TSSOP
38-pin TSSOP
38-pin TSSOP
38-pin TSSOP
44-pin PQFP
44-pin PQFP
Test Inputs
Yes
Yes
No
No
Yes
Yes
Temperature
Range
− 55 / + 85oC
− 55 / + 125oC
− 55 / + 85oC
− 55 / + 125oC
− 55 / + 85oC
− 55 / + 125oC
HOLT INTEGRATED CIRCUITS
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HI-8456 datasheet pdf
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