HD74LV2GT74A Datasheet PDF - Renesas Technology

www.Datasheet-PDF.com

HD74LV2GT74A
Renesas Technology

Part Number HD74LV2GT74A
Description Single D-type Flip Flops
Page 10 Pages


HD74LV2GT74A datasheet pdf
Download PDF
HD74LV2GT74A pdf
View PDF for Mobile

No Preview Available !

www.DataSheet4U.com
HD74LV2GT74A
Single D–type Flip Flops with Preset and Clear /
CMOS Logic Level Shifter
REJ03D0146–0200Z
(Previous ADE-205-681A (Z))
Rev.2.00
Oct.17.2003
Description
The HD74LV2GT74A has independent data, preset, clear, and clock inputs Q and Q outputs in an 8 pin
package. The input data is transferred to the output at the rising edge of clock pulse CLK. The input
protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used
as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to
3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed
operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.
Features
The basic gate function is lined up as Renesas uni logic series.
Supplied on emboss taping for high-speed automatic mounting.
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
Logic-level translate function
3.0 V CMOS logic 5.0 V CMOS logic (@VCC = 5.0 V)
1.8 V or 2.5 V CMOS logic 3.3 V CMOS logic (@VCC = 3.3 V)
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
All the logical input has hysteresis voltage for the slow transition.
Ordering Information
Part Name
Package Type
HD74LV2GT74AUSE SSOP-8 pin
Package Code
TTP-8DBV
Package
Abbreviation
US
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Rev.2.00, Oct.17.2003, page 1 of 1



No Preview Available !

www.DataSheet4U.com
HD74LV2GT74A
Outline and Article Indication
• HD74LV2GT74A
Index band
Lot No.
YMW
T74
Y : Year code
(the last digit of year)
M : Month code
W : Week code
SSOP–8
Marking
Function Table
Inputs
Outputs
PRE
CLR
CLK
D
Q
Q
L HXXHL
HL XXL H
L
L
X
X
H *1
H *1
HHHHL
HHL L H
H H X Q0 Q0
H : High level
L : Low level
X : Immaterial
: Low to high transition
: High to low transition
Q0 : The level of Q immediately before the input conditions shown in the above table are determined.
Note : 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if
preset and clear go high simultaneously.
Rev.2.00, Oct.17.2003, page 2 of 9



No Preview Available !

www.DataSheet4U.com
HD74LV2GT74A
Pin Arrangement
CLK 1
D2
Q3
GND 4
8 VCC
7 PRE
6 CLR
5Q
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit Test Conditions
Supply voltage range
Input voltage range *1
Output voltage range *1, 2
VCC
VI
VO
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
Maximum power dissipation
at Ta = 25°C (in still air) *3
IIK
IOK
IO
ICC or IGND
PT
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±25
±50
200
V
V
V Output : H or L
VCC : OFF
mA VI < 0
mA VO < 0 or VO > VCC
mA VO = 0 to VCC
mA
mW
Storage temperature
Tstg
–65 to 150
°C
Notes:
The absolute maximum ratings are values, which must not individually be exceeded, and
furthermore no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.2.00, Oct.17.2003, page 3 of 9



No Preview Available !

www.DataSheet4U.com
HD74LV2GT74A
Recommended Operating Conditions
Item
Symbol
Ratings
Supply voltage
VCC 3.0 to 5.5
Input voltage
VIN 0 to 5.5
Output voltage
VOUT
0 to VCC
Operating temperature
Topr
–40 to +85
Input rise / fall time
tr, tf 0 to 100 (VCC = 3.0 to 3.6 V)
0 to 20 (VCC = 4.5 to 5.5 V)
Note: Unused or floating inputs must be held high or low.
Unit
V
V
V
°C
ns
Logic Diagram
PRE
CLK
C
C
D
CLR
C
TG
C
C
TG
C
C
TG
CC
TG
C
Q
Q
Rev.2.00, Oct.17.2003, page 4 of 9



HD74LV2GT74A datasheet pdf
Download PDF
HD74LV2GT74A pdf
View PDF for Mobile


Related : Start with HD74LV2GT74 Part Numbers by
HD74LV2GT74A Single D-type Flip Flops HD74LV2GT74A
Renesas Technology
HD74LV2GT74A pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Contact