HD74LV2GT245A Datasheet PDF - Renesas Technology

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HD74LV2GT245A
Renesas Technology

Part Number HD74LV2GT245A
Description Dual Bus Transceivers
Page 10 Pages


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HD74LV2GT245A
Dual Bus Transceivers with 3–state Outputs /
CMOS Logic Level Shifter
REJ03D0153–0200Z
(Previous ADE-205-694A (Z))
Rev.2.00
Oct.23.2003
Description
The HD74LV2GT245A has two buffers with three state output in a 8 pin package. When DIR is high, data
is transferred from the A inputs to the B outputs, and when DIR is low, data is transferred from the B inputs
to the A outputs. The A and B buses are separated by making the enable input (OE) high level. The input
protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used
as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to
3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed
operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.
Features
The basic gate function is lined up as Renesas uni logic series.
Supplied on emboss taping for high-speed automatic mounting.
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
Logic-level translate function
3.0 V CMOS logic 5.0 V CMOS logic (@VCC = 5.0 V)
1.8 V or 2.5 V CMOS logic 3.3 V CMOS logic (@VCC = 3.3 V)
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V, Output : Z)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
All the logical input has hysteresis voltage for the slow transition.
Ordering Information
Part Name
Package Type
HD74LV2GT245AUSE SSOP-8 pin
Package Code
TTP-8DBV
Package
Abbreviation
US
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Rev.2.00, Oct.23.2003, page 1 of 9



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HD74LV2GT245A
Outline and Article Indication
• HD74LV2GT245A
Index band
Lot No.
SSOP-8
Function Table
Inputs
OE
L
L
H
H : High level
L : Low level
X : Immaterial
DIR
L
H
X
YMW
T45
Y : Year code
(the last digit of year)
M : Month code
W : Week code
Marking
Operation
B data to A bus
A data to B bus
Isolation
Rev.2.00, Oct.23.2003, page 2 of 9



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HD74LV2GT245A
Pin Arrangement
DIR 1
A1 2
A2 3
GND 4
8 VCC
7 OE
6 B1
5 B2
(Top view)
Absolute Maximum Ratings
Item
Symbol Ratings
Unit Test Conditions
Supply voltage range
Input voltage range *1
Output voltage range *1, 2
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
Maximum power dissipation
at Ta = 25°C (in still air) *3
VCC
VI
VO
IIK
IOK
IO
ICC or IGND
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
±50
±25
±50
PT 200
V
V
V Output : H or L
VCC : OFF or output : Z
mA VI < 0
mA VO < 0 or VO > VCC
mA VO = 0 to VCC
mA
mW
Storage temperature
Tstg –65 to 150
°C
Notes:
The absolute maximum ratings are values, which must not individually be exceeded, and
furthermore no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.2.00, Oct.23.2003, page 3 of 9



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HD74LV2GT245A
Recommended Operating Conditions
Item
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise / fall time
Symbol
VCC
VIN
VOUT
Topr
tr, tf
Ratings
Unit Test Conditions
3.0 to 5.5
V
0 to 5.5
V
0 to VCC
0 to 5.5
V
Output : Z
–40 to +85
°C
0 to 100 (VCC = 3.0 to 3.6 V) ns
0 to 20 (VCC = 4.5 to 5.5 V)
Rev.2.00, Oct.23.2003, page 4 of 9



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