HD74LV2G74A Datasheet PDF - Hitachi Semiconductor

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HD74LV2G74A
Hitachi Semiconductor

Part Number HD74LV2G74A
Description Single D-type Flip Flops
Page 12 Pages


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HD74LV2G74A
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Single D–type Flip Flops with Preset and Clear
ADE-205-346C (Z)
Rev.3
July 2001
Description
The HD74LV2G74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 8 pin
package. The input data is transferred to the output at the rising edge of clock pulse CLK. Low voltage
and high speed operation is suitable for the battery powered products (e.g., notebook computers), and the
low power consumption extends the battery life.
Features
The basic gate function is lined up as hitachi uni logic series.
Supplied on emboss taping for high speed automatic mounting.
Electrical characteristics equivalent to the HD74LV74A
Supply voltage range : 1.65 to 5.5 V
Operating temperature range : –40 to +85°C
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
All the logical input has hysteresis voltage for the slow transition.



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HD74LV2G74A
Outline and Article Indication
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• HD74LV2G74A
Index band
Lot No.
YMW
L74
Y : Year code
(the last digit of year)
M : Month code
W : Week code
SSOP–8
Type No.
Function Table
Inputs
Outputs
PRE
CLR
CLK
D
Q
Q
L HXXHL
HL XXL H
L
L
X
X
H *1
H *1
HHHHL
HHL L H
H H X Q0 Q0
H : High level
L : Low level
X : Immaterial
: Low to high transition
: High to low transition
Q : The level of Q immediately before the input conditions shown in the above table are determined.
0
Note : 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if
preset and clear go high simultaneously.
Rev.3, Jul. 2001, page 2 of 12



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Pin Arrangement
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HD74LV2G74A
CLK 1
D2
Q3
GND 4
8 VCC
7 PRE
6 CLR
5Q
(Top view)
Rev.3, Jul. 2001, page 3 of 12



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HD74LV2G74A
Absolute Maximum Ratings
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Item
Symbol
Ratings
Unit Test Conditions
Supply voltage range
Input voltage range *1
Output voltage range *1, 2
V
CC
VI
V
O
Input clamp current
Output clamp current
Continuous output current
Continuous current through
VCC or GND
Maximum power dissipation
at Ta = 25°C (in still air) *3
IIK
IOK
IO
ICC or IGND
PT
–0.5 to 7.0
–0.5 to 7.0
–0.5 to V + 0.5
CC
–0.5 to 7.0
–20
±50
±25
±50
200
V
V
V Output : H or L
V : OFF
CC
mA VI < 0
mA VO < 0 or VO > VCC
mA VO = 0 to VCC
mA
mW
Storage temperature
Tstg
–65 to 150
°C
Notes:
The absolute maximum ratings are values which must not individually be exceeded, and
furthermore no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.3, Jul. 2001, page 4 of 12



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