GS74116ATP Datasheet PDF - GSI Technology

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GS74116ATP
GSI Technology

Part Number GS74116ATP
Description 256K x 16 4Mb Asynchronous SRAM
Page 14 Pages


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GS74116ATP/J/X
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
256K x 16
4Mb Asynchronous SRAM
7, 8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 150/130/105/95 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
X: 6 mm x 10 mm Fine Pitch Ball Grid Array
package
Description
The GS74116A is a high speed CMOS Static RAM organized
as 262,144 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS74116A is available in a 6 x 10 mm Fine
Pitch BGA package, 400 mil SOJ and 400 mil TSOP Type-II
packages.
SOJ 256K x 16-Pin Configuration (Package J)
A4 1
A3 2
A2 3
A1 4
A0 5
Top view
CE 6
DQ1 7
DQ2 8
DQ3 9
DQ4 10
VDD 11
44-pin
VSS 12
DQ5 13
SOJ
DQ6 14
DQ7 15
DQ8 16
WE 17
A15 18
A14 19
A13 20
A12 21
A16 22
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 DQ16
37 DQ15
36 DQ14
35 DQ13
34
33
32
VSS
VDD
DQ12
31 DQ11
30 DQ10
29 DQ9
28 NC
27 A8
26 A9
25 A10
24 A11
23 A17
Pin Descriptions
Symbol
A0–A17
DQ1–DQ16
CE
LB
UB
WE
OE
VDD
VSS
NC
Description
Address input
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
Upper byte enable input
(DQ9 to DQ16)
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
FP-BGA 256K x 16 Bump Configuration (Package X)
123456
A LB OE A0 A1 A2 NC
B DQ16 UB A3 A4 CE DQ1
C DQ14 DQ15 A5 A6 DQ2 DQ3
D VSS DQ13 A17 A7 DQ4 VDD
E VDD DQ12 NC A16 DQ5 VSS
F DQ11 DQ10 A8 A9 DQ7 DQ6
G DQ9 NC A10 A11 WE DQ8
H NC A12 A13 A14 A15 NC
6 x 10 mm Bump Pitch
Rev: 1.03 10/2002
1/14
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.



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Top View
TSOP-II 256K x 16 Pin Configuration (Package TP)
A4 1
A3 2
A2 3
A1 4
Top view
A0 5
CE 6
DQ1 7
DQ2 8
DQ3 9
DQ4 10
VDD 11
44 pin
VSS
DQ5
12
13
TSOP II
DQ6 14
DQ7 15
DQ8 16
WE 17
A15 18
A14 19
A13 20
A12 21
A16 22
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 DQ16
37 DQ15
36 DQ14
35
34
33
32
31
DQ13
VSS
VDD
DQ12
DQ11
30 DQ10
29 DQ9
28 NC
27 A8
26 A9
25 A10
24 A11
23 A17
Block Diagram
A0 Row
Address Decoder
Input
Buffer
A17
CE
WE
OE
Control
UB _____
LB _____
Memory Array
Column
Decoder
I/O Buffer
DQ1 DQ16
GS74116ATP/J/X
Rev: 1.03 10/2002
2/14
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.



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GS74116ATP/J/X
Truth Table
CE OE WE LB UB
HXXXX
LL
LLHLH
HL
LL
LXLLH
HL
LHHXX
L X XHH
Note: X: “H” or “L”
DQ1 to DQ8
Not Selected
Read
Read
High Z
Write
Write
Not Write, High Z
High Z
High Z
DQ9 to DQ16
Not Selected
Read
High Z
Read
Write
Not Write, High Z
Write
High Z
High Z
VDD Current
ISB1, ISB2
IDD
Absolute Maximum Ratings
Parameter
Supply Voltage
Input Voltage
Output Voltage
Allowable power dissipation
Storage temperature
Symbol
VDD
VIN
VOUT
PD
TSTG
Rating
–0.5 to +4.6
–0.5 to VDD +0.5
(4.6 V max.)
–0.5 to VDD +0.5
(4.6 V max.)
0.7
–55 to 150
Unit
V
V
V
W
oC
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec-
ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Rev: 1.03 10/2002
3/14
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.



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GS74116ATP/J/X
Recommended Operating Conditions
Parameter
Supply Voltage for -7/-8/-10/-12
Input High Voltage
Input Low Voltage
Ambient Temperature,
Commercial Range
Ambient Temperature,
Industrial Range
Symbol
VDD
VIH
VIL
TAc
TAI
Min
3.0
2.0
–0.3
0
–40
Typ
3.3
Note:
1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Max
3.6
VDD +0.3
0.8
70
85
Unit
V
V
V
oC
oC
Capacitance
Parameter
Symbol
Test Condition
Input Capacitance
Output Capacitance
CIN
COUT
VIN = 0 V
VOUT = 0 V
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
Max
5
7
Unit
pF
pF
DC I/O Pin Characteristics
Parameter
Symbol
Input Leakage
Current
IIL
Output Leakage
Current
Output High Voltage
Output Low Voltage
ILO
VOH
VOL
Test Conditions
VIN = 0 to VDD
Output High Z
VOUT = 0 to VDD
IOH = –4 mA
ILO = +4 mA
Min
– 1 uA
–1 uA
2.4
Max
1 uA
1 uA
0.4 V
Rev: 1.03 10/2002
4/14
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, Giga Semiconductor, Inc.



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