G2237-208-041PTB2 Datasheet PDF - GlobespanVirata



Part Number G2237-208-041PTB2
Description Transceiver
Page 30 Pages

G2237-208-041PTB2 datasheet pdf
View PDF for PC
G2237-208-041PTB2 pdf
View PDF for Mobile

No Preview Available !

June 25, 2002, Issue 2
Part Numbers
G2216-208-041PF B2 (SDSL 2B1Q)
G2214-208-041DF B2 (SDSL CAP)
G2237-208-041PT B2 (SHDSL/HDSL2)
G2237-208-041PT C1 (SHDSL/HDSL2)
Dual-Channel, Low Power, Programmable
Transceiver with Integrated Framer and Line Drivers
Data Sheet
The GlobespanVirata® XDSL2™ Digital Subscriber Line
(DSL) chip sets provide low power, high density solutions for
2-wire DSL equipment. These chip sets are fully
programmable and field upgradeable eliminating the risk of
product obsolescence and accelerating the time-to-market for
new network services. The GlobespanVirata® XDSL2™ DSL
chip sets are fully interoperable with multi-vendor DSL chip
set solutions. This interoperability enables dynamic
interworking of multiple vendor DSL solutions with the
capability to interoperate with products that conform to ANSI
and ETSI DSL standards.
GlobespanVirata’s unique hardware platform supports
multiple dual-channel applications including SDSL, HDSL2,
and SHDSL, using population options for optimization.
The XDSL2 DSL chip sets incorporate two DSL bit pumps
plus framing into a three-chip solution comprised of a dual-
channel digital signal processor (DSP) with built-in framer and
two Analog Front Ends each with an Integrated Line Driver
The XDSL2 chip sets interface directly with off-the-shelf T1/
E1 transceivers and Nx64 multiplexing, eliminating the need
for a separate DSL framer to combine and format the two DSL
channels into a standard interface. GlobespanVirata’s DSL
XDSL2 chip sets deliver two channels of full duplex
transmission up to 2320 kb/s, depending on the application.
The high density XDSL2 dual-channel DSL chip sets are ideal
for CO applications, while single-channel versions with
integrated framer are also available for CPE applications.
Dual-channel DSP with framer that fully integrates
2 separate DSL chips into a single device
Two AFEs, each with an integrated differential line driver
2B1Q, CAP, or PAM line codes
Supports dual-channel symmetric data rates of 144 kb/s
to 2320 kb/s (depending on the application)
Supports IDSL with optional data interface rates of
64 kb/s, 128 kb/s, and 144 kb/s
Offers physical layer interoperability with competitive solu-
Glueless interface to popular microprocessors
Transmission compliant with ETSI TS 101 135, ITU-T
G.991.1, and ANSI TR-28 for single pair 2B1Q and CAP,
ANSI T1.418 for HDSL2 and ITU-T G.991.2 for SHDSL
Reference design compatible with Bellcore GR-1089, IEC
60950, UL 1950, ITU-T K.20 and K.21
Built-in framer provides easy access to EOC and indicator
bits (framing can be bypassed completely for 2-channel
independent operation)
Interfaces directly with off-the-shelf single-channel T1/E1
ATM UTOPIA Level 1 and 2 interface
A single oscillator and hybrid topology supports all speeds
+3.3V and +5V power supplies
Customer Interface
TClock (A/B)
Frame Pulse (A/B)
Rclock (A/B)
Frame Pulse (A/B)
µ Processor Interface
Figure 1. Block Diagram of XDSL2™ DSP with Two Single-Channel ILD2s
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions
DO-009643-DS, Issue 2

No Preview Available !

XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
June 25, 2002
The GlobespanVirata DSL chip sets support
applications ranging from remote network access,
digital pair gain, video conferencing, and cellular base
station land-line connectivity, for T1/E1 services. Up to
36 voice circuits may be provisioned over a single
copper pair.
Example Applications
Compatibility with voice/data pair gain systems
Cellular and microcellular systems
T1/E1 and fractional T1/E1 DSL transceiver
Wireless base station connectivity
Related Materials
To accelerate time-to-market, GlobespanVirata offers
our customers a comprehensive Design Guide which
includes details on planning, layout, testing, debugging,
and expert tips and recommendations for building a
successful DSL product. The Design Guide is
distributed as part of a Design Package which includes
firmware, transceiver schematics, sample code,
transceiver layout Gerber files, and Bill of Materials.
For rapid prototyping, Quick Kits are available. These
Quick Kits contain all transceiver design BOM
components in kit form so there’s no component lead
time delay.
The Super GlobespanVirata Development System
(SGDSTM), an easy-to-use evaluation and development
platform designed to support all GlobespanVirata xDSL
transceiver solutions, is also available for early product
The SGDS also provides an interface to the
GlobespanVirata Microsoft® Windows® - based Host
Interface Program (WHIP). When the SGDS is teamed
with WHIP, product evaluation, testing and debugging is
achieved with the click of a mouse.
GlobespanVirata Transceiver System
The GlobespanVirata XDSL2™ DSL chip sets con-
sist of a dual-channel DSP with an on-chip framer,
and two single-channel AFEs (with ILD2).
The single-channel ILD2s filter and digitize the sig-
nal received on the telephone line and for the trans-
mit side, generate analog signals from the digital
data and filter the analog signals to create the
2B1Q, CAP or PAM transmit signal (depending on
the line code).
The GlobespanVirata Windows-based Host Inter-
face Program (WHIP) is offered as part of the
GlobespanVirata transceiver system development
package for SDSL 2B1Q, HDSL2, and SHDSL
applications. WHIP allows you to test and debug
your product design with the click of a mouse. This
graphical interface allows you to send commands,
perform trace and debug procedures, and initiate a
startup on both the CO and CP units. WHIP offers
complete flexibility and modularity - you can rear-
range windows and toolbars to suit your prefer-
ences and design requirements.
SDSL CAP applications are offered the Globespan-
Virata Host Interface Program (HIP) software as
part of the GlobespanVirata transceiver system
development package. The PC-based HIP software
provides a PC interface to the host. HIP allows the
host to run scripts to obtain and manipulate data,
test performance, and debug the software. No addi-
tional software or special PC hardware or tools are
required. Customers who use HIP with their host
processor receive the benefits of faster diagnosis
and specialized assistance from the GlobespanVi-
rata staff.
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions
DO-009643-DS, Issue 2

No Preview Available !

June 25, 2002
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
The interface between the Host and the transceiver
consists of the following:
Transmission Interface (data, clock and synchronization
Control Interface (microprocessor compatible)
Diagnostic Interface
Power Interface
Loop Interface
System timing is derived from a free running oscillator
in the transceiver of the central office (CO). At the
customer premises end (CPE), the CPE derives a clock
from the received line signal and provides this clock to
the CPE transmitter.
The dual-channel chip set also supports Network
Timing Recovery (NTR) at the CO end. With this feature
enabled, the CO unit will accept a clock at 8 kHz (± 100
ppm) as an input and the STU-R will output a clock that
is phase locked to the CO clock. The NTR clock should
have a duty cycle of 45-55%. Note that this feature is
only available with an UTOPIA interface.
The DSL transceiver supports both T1 and E1 rates,
and fractional rates.
Transceiver States
The following is a list of the possible states that the DSL
transceiver can be in:
IDLE mode, where the transceiver is not attempting
to start up, pass data, or perform tests
TEST mode, where the transceiver is either in local
analog loopback or local digital loopback and is not
passing user data
STARTUP mode (SDSL only), where the trans-
ceiver is attempting a startup of the DSL connec-
tion, prior to entering DATA mode
HANDSHAKE mode (HDSL2 and SHDSL), where a
link is established between the CO unit and the
CPE unit
TRAINING mode (HDSL2 and SHDSL), where the
transceiver is attempting a startup, prior to entering
DATA mode
DATA mode, where the transceiver has started up
and trained and is capable of passing user data
Software Interface
A microprocessor interface that uses simple read/write
drivers provides direct access to the GlobespanVirata
chip set—eliminating the need for complicated register
maps and advanced programming. These drivers allow
the Host to select rates, adjust transmit power, read
signal quality, and perform a variety of other tasks
which include reporting the current operational status of
the transceiver.
To configure and control the transceiver,
GlobespanVirata provides hardware-dependent driver
examples and GlobespanVirata supplied transceiver
software modules (TSMs). The TSMs have the ability to
allow a single CPU in the Host to control multiple
transceivers. This could be a potential cost savings for
arrangements where it might be advantageous to put
multiple transceivers on one card, such as at the CO.
You will not need a register map of the DSP, as this
information is not required to successfully design
and implement an STU. As discussed previously,
access to the DSP is provided through hardware-
dependent I/O routines and GlobespanVirata
provided TSMs.
DO-009643-DS, Issue 2
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions

No Preview Available !

XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
June 25, 2002
Data Mode
Power Up
Power Up
Reset DSP
Idle Mode
Idle Mode
Set all
Idle Mode
DSP/Framer Interrupt Received
Power Up/
Reset DSP
Start Up
Host Processes GTI_ACTIVE
Data Mode
May occur anytime
before Data Mode.
(not timed)
* Only if PLL is enabled
Figure 2. Typical Transceiver Power Up/Start Up
Transceiver Power Up Sequence
Figure 2 describes a typical sequence from power up to
DATA mode for a transceiver. After power is applied to
both the Host and the transceiver, the Host calls the
InitXCVR_CS() and InitXCVR() routines to
initialize transceiver variables and to initialize the DSP/
Next, the Host calls the SetParamXCVR() routine to
set up the parameters that are appropriate for start up of
the transceiver.
The SetParamFramer() routine is called by the Host
to initialize framer options.
After setting up the transceiver parameters, the Host
calls the ExecuteXCVR() routine to execute the
command that was set up using the SetParamXCVR()
routine. With a successful completion of the
ExecuteXCVR() routine, the transceiver will now be in
DATA mode.
The SStatusXCVR() routine is used to track
performance and to obtain information from the
transceiver about what state the transceiver is in (i.e.,
monitor start-up, check signal quality, etc.).
Setting Up the Command Parameters
The routine SetParamXCVR() processes the
parameter array structure that will be executed when
the ExecuteXCVR() routine is called.
The parameter structure will be similar to the following
start-up example:
struct PARAM_XCVR_ARRAY Items;
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions
DO-009643-DS, Issue 2

G2237-208-041PTB2 datasheet pdf
Download PDF
G2237-208-041PTB2 pdf
View PDF for Mobile

Related : Start with G2237-208-041PTB Part Numbers by
G2237-208-041PTB2 Transceiver G2237-208-041PTB2
G2237-208-041PTB2 pdf

Index :   0   1   2   3   4   5   6   7   8   9   A   B   C   D   E   F   G   H   I   J   K   L   M   N   O   P   Q   R   S   T   U   V   W   X   Y   Z   

This is a individually operated, non profit site. If this site is good enough to show, please introduce this site to others.
Since 2010   ::   HOME   ::   Privacy Policy + Contact