ESD8116 Datasheet PDF - ON Semiconductor

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ESD8116
ON Semiconductor

Part Number ESD8116
Description ESD Protection Diode
Page 12 Pages


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ESD8116
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8116 transient voltage suppressor is specifically designed
to protect USB 3.0/3.1 interfaces from ESD. Ultra−low capacitance
and low ESD clamping voltage make this device an ideal solution for
protecting voltage sensitive high speed data lines. The flow−through
style package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines.
Features
Low Capacitance (0.35 pF Max, I/O to GND)
Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
Low ESD Clamping Voltage
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
USB 3.0/3.1
Display Port
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range TJ −55 to +125 °C
Storage Temperature Range
Tstg − 55 to +150 °C
Lead Solder Temperature −
Maximum (10 Seconds)
TL 260 °C
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
ESD
ESD
±15 kV
±15 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
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UDFN8
CASE 517CX
MARKING
DIAGRAM
6CMG
G
6C = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
I/O I/O I/O I/O
8 76 5
12
I/O GND
34
GND I/O
ORDERING INFORMATION
Device
Package
Shipping
ESD8116MUTAG UDFN8 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 0
1
Publication Order Number:
ESD8116/D



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ESD8116
I/O I/O I/O I/O I/O I/O
Pin 1 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8
Pins 2, 3
Note: Common GND − Only Minimum of 1 GND connection required
=
Figure 1. Pin Schematic
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ESD8116
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol
Parameter
IPP Maximum Peak Pulse Current
VC Clamping Voltage @ IPP
VRWM Working Peak Reverse Voltage
IR Maximum Reverse Leakage Current @ VRWM
VBR Breakdown Voltage @ IT
IT Test Current
RDYN
Dynamic Resistance
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
I
IPP
RDYN
VCL VBR VRWM
IIRT
VCL
RDYN
IPP
Uni−Directional TVS
V
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Symbol
Conditions
Min Typ Max Unit
Reverse Working Voltage
Breakdown Voltage
Reverse Leakage Current
Clamping Voltage
(Note 1)
VRWM
VBR
IR
VC
I/O Pin to GND
IT = 1 mA, I/O Pin to GND
VRWM = 3.3 V, I/O Pin to GND
IEC61000−4−2, ±8 kV Contact
3.3
4.0 5.0
1.0
See Figures 2 and 3
V
V
mA
V
Clamping Voltage
TLP (Note 2)
See Figures 6 through 9
VC IPP = 8 A
IPP = −8 A
IPP = 16 A
IPP = −16 A
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact, ±4 kV Air)
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact, ±15 kV Air)
8.5 V
−4.5
11.4
−8.0
Dynamic Resistance
RDYN I/O Pin to GND
GND to I/O Pin
0.36 W
0.44
Junction Capacitance
CJ VR = 0 V, f = 1 MHz between I/O Pins and GND
VR = 0 V, f = 1 MHz between I/O Pins
VR = 0 V, f = 1 MHz, TA = 65°C between I/O Pins and GND
0.30 0.35 pF
0.15 0.20
0.37 0.47
1. For test procedure see Figures 4 and 5 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
90
80
70
60
50
40
30
20
10
0
−10
−20
0 20 40 60 80 100 120 140
TIME (ns)
Figure 2. IEC61000−4−2 +8 kV Contact
Clamping Voltage
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−20
0 20 40 60 80 100 120
TIME (ns)
Figure 3. IEC61000−4−2 −8 kV Contact
Clamping Voltage
140
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ESD8116
IEC 61000−4−2 Spec.
Level
First Peak
Test Volt- Current Current at
age (kV)
(A) 30 ns (A)
1 2 7.5 4
2 4 15 8
3 6 22.5 12
48
30 16
Current at
60 ns (A)
2
4
6
8
IEC61000−4−2 Waveform
Ipeak
100%
90%
I @ 30 ns
I @ 60 ns
10%
Figure 4. IEC61000−4−2 Spec
tP = 0.7 ns to 1 ns
ESD Gun
TVS
Oscilloscope
50 W
Cable
50 W
Figure 5. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8307/D − Characterization of ESD Clamping
Performance.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
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