EP82562G Datasheet PDF - Intel

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EP82562G
Intel

Part Number EP82562G
Description 10/100 Mbps Platform LAN Connect
Page 30 Pages


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h8Ce2eo5tn46nU2e.Gccotm1(0P/1L0C0) Mbps Platform LANNetworking Silicon
.DataS Product Features
Datasheet
ww IEEE 802.3 10BASE-T/100BASE-TX
w compliant physical layer interface
mIEEE 802.3u Auto-Negotiation support
Digital Adaptive Equalization control
oLink status interrupt capability
.cXOR tree mode support
3-port LED support (speed, link and
activity)
U10BASE-T auto-polarity correction
t4LAN Connect Interface
Diagnostic loopback mode
1:1 transmit transformer ratio support
Low power (less than 300 mW in active
transmit mode)
Reduced power in “unplugged mode” (less
than 50 mW)
Automatic detection of “unplugged mode”
3.3 V device
Lead-free1 48-pin Shrink Small Outline
Package for both leaded and lead-free
designs. (Devices that are lead-free are
marked with a circled “e3” and have the
product code prefix: LUxxxxxx).
e1 This device is lead-free. That is, lead has not been intentionally added, but lead may still exist
eas an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead
himpurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-
banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks
SIn addition, this device has been tested and conforms to the same parametric specifications as
taprevious versions of the device.
For more information regarding lead-free products from Intel Corporation, contact your Intel
aField Sales representative.
.DAdditional Features
The 82562G PLC supports drop-in replacement with the 82562ET. If it is not used as a drop-
in replacement, strapping options enable new operating modes:
w—LED support for three logic configurations.
— LAN disable function using one pin.
w—Increased transmit strength.
mThe receive BER performance increases the margin for cable length.
w oReturn Loss performance is improved.
.DataSheet4U.cRevision 1.2
www January 2005



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Revision History
Revision
1.0
1.1
1.2
Revision Date
Description
January 2005 Initial release (confidential status).
November 2004
• Updated lead-free device information.
• Updated Table 1 and Table 2 to reflect correct hardware configurations
and LED logic functionality.
• Corrected signal names to match design guide and reference schemat-
ics.
January 2005 • Added a note for PHY signals RBIAS100 and RBIAS10 to Section 4.3.
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82562G PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2004, Intel Corporation
* Other brands and names are the property of their respective owners.
Datasheet



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82562G — Networking Silicon
Contents
1.0
1.1
1.2
1.3
Introduction......................................................................................................................... 1
Overview ...................................................................................................................... 1
References................................................................................................................... 1
Product Codes ............................................................................................................. 1
2.0 82562G Architectural Overview.......................................................................................... 3
2.1
2.1.1
2.1.2
2.1.3
2.2
LAN Connect Interface.................................................................................................3
Reset/Synchronize Operations ..............................................................................4
Reset Considerations ............................................................................................ 4
LAN Connect Clock Operations............................................................................. 5
Hardware Configuration ............................................................................................... 5
3.0 Performance Enhancements.............................................................................................. 7
3.1
3.1.1
3.1.2
New Usage Modes: 1, 2, 3, and 4................................................................................ 7
Pin Usage for Modes 1, 2, 3, and 4 .......................................................................7
Enhanced Tx Mode................................................................................................ 8
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
82562G Signal Descriptions............................................................................................... 9
Signal Type Definitions ............................................................................................... 9
Twisted Pair Ethernet (TPE) Pins ............................................................................... 9
External Bias Pins ....................................................................................................... 9
Clock Pins .................................................................................................................10
Platform LAN Connect Interface Pins .......................................................................10
LED Pins ...................................................................................................................11
Miscellaneous Control Pins .......................................................................................11
Power and Ground Connections ...............................................................................12
5.0 Physical Layer Interface Functionality..............................................................................13
5.1
5.1.1
5.1.2
5.2
5.2.1
5.2.2
5.3
5.4
5.4.1
5.4.2
5.4.3
100BASE-TX Mode....................................................................................................13
100BASE-TX Transmit Blocks.............................................................................13
100BASE-TX Receive Blocks..............................................................................15
10BASE-T Mode ........................................................................................................16
10BASE-T Transmit Blocks .................................................................................16
10BASE-T Receive Blocks ..................................................................................16
Analog References.....................................................................................................17
Dynamic Reduced Power & Auto Plugging Detection................................................17
Auto Plugging Detection ......................................................................................18
Dynamic Reduced Power ....................................................................................18
Configuration .......................................................................................................18
6.0 Platform LAN Connect Registers .....................................................................................19
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Medium Dependent Interface (MDI) Registers 0 through 7 .......................................19
Register 0: Control Register Bit Definitions ........................................................19
Register 1: Status Register Bit Definitions ..........................................................20
Register 2: PHY Identifier Register Bit Definitions ..............................................21
Register 3: PHY Identifier Register Bit Definitions ..............................................21
Register 4: Auto-Negotiation Advertisement Register Bit Definitions .................21
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82562G — Networking Silicon
6.1.6
6.1.7
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions .......... 22
Register 6: Auto-Negotiation Expansion Register Bit Definitions ....................... 22
MDI Registers 8 through 15 ....................................................................................... 23
MDI Registers 16 through 31 ..................................................................................... 23
Register 16: PHY Status and Control Register Bit Definitions ............................ 23
Register 17: PHY Unit Special Control Bit Definitions ........................................ 24
Register 18: Reserved ........................................................................................ 24
Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions ......... 25
Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions ............ 25
Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions ........... 25
Register 22: Receive Symbol Error Counter Bit Definitions ............................... 25
Register 23: 100BASE-TX Receive Premature End of Frame
Error Counter Bit Definitions ............................................................................... 25
Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions .... 26
Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions ........... 26
Register 27: PHY Unit Special Control Bit Definitions ........................................ 27
7.0
7.1
7.2
82562G Test Port Functionality........................................................................................ 29
Asynchronous Test Mode .......................................................................................... 29
Test Function Description .......................................................................................... 29
8.0 Electrical and Timing Specifications................................................................................. 31
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.3
8.3.1
8.3.2
8.3.3
8.3.4
Absolute Maximum Ratings ....................................................................................... 31
DC Characteristics .................................................................................................... 31
X1 Clock DC Specifications ................................................................................ 31
LAN Connect Interface DC Specifications .......................................................... 32
LED DC Specifications ....................................................................................... 32
10BASE-T Voltage and Current DC Specifications ............................................ 32
100BASE-TX Voltage and Current DC Specifications ........................................ 33
AC Characteristics ..................................................................................................... 34
10BASE-T Normal Link Pulse (NLP) Timing Parameters ................................... 34
Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters .............................. 35
100BASE-TX Transmitter AC Specifications ...................................................... 36
Reset (RSTSYNC) AC Specifications ................................................................ 36
9.0 Package and Pinout Information ...................................................................................... 37
9.1
9.2
9.2.1
9.2.2
Package Information .................................................................................................. 37
Pinout Information ...................................................................................................... 38
82562G Pin Assignments ................................................................................... 38
82562G Shrink Small Outline Package Diagram ................................................ 39
ii Datasheet



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