EP5362Q Datasheet PDF - Enpirion


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EP5362Q
Enpirion

Part Number EP5362Q
Description (EP5352Q - EP5382Q) 500/600/800mA Synchronous Buck Regulators
Page 16 Pages

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EP5352Q/EP5362Q/EP5382Q
500/600/800mA Synchronous Buck Regulators
With Integrated Inductor
RoHS Compliant
ENABLE
UVLO
Thermal Limit
Current Limit
Soft Start
(-)
PWM
Comp
(+)
Sawtooth
Generator
VIN
Logic
P-Drive
N-Drive
Compensation
Network
(-)
Error
Amp
(+)
VREF
DAC
Switch
VOUT
GND
VSENSE
VFB
Voltage
Select
Package Boundry
VS0 VS1 VS2
Product Highlights
Revolutionary integrated inductor
Very small solution foot print*
Fully RoHS compliant; MSL 3 260°C reflow
Only two low cost components required
5mm x 4mm x1.1mm QFN package
Wide 2.4V to 5.5V input range
500, 600, 800 mA output current versions
Less than 1 μA standby current
4 MHz switching frequency
Fast transient response
Very low ripple voltage; 5mVp-p typical
3 Pin VID Output Voltage select
External divider option
Dynamically adjustable output
Designed for Low noise/EMI
Short circuit, UVLO, and thermal protection
Product Overview
The Ultra-Low-Profile EP53X2Q product family is
targeted to applications where board area and
profile are critical. EP53X2Q is a complete power
conversion solution requiring only two low cost
ceramic MLCC caps. Inductor, MOSFETS,
PWM, and compensation are integrated into a
tiny 5mm x 4mm x 1.1mm QFN package. The
EP53x2Q family is engineered to simplify design
and to minimize layout constraints. High
switching frequency and internal type III
compensation provides superior transient
response. With a 1.1 mm profile, the EP53x2 is
perfect for space and height limited applications.
A 3-pin VID output voltage select scheme
provides seven pre-programmed output voltages
along with an option for external resistor divider.
Output voltage can be programmed on-the-fly to
provide fast, dynamic voltage scaling.
Typical Application Circuit
VIN
2.2uF
Voltage
Select
ENABLE
Vin
VSense
Vout
VS0 VFB
VS1
VS2 GND
VOUT
10μF
Figure 1. Typical application circuit.
Applications
Area constrained applications
Mobile multimedia, smartphone & PDA
Mobile and Cellular platforms
VoIP and Video phones
Personal Media Players
FPGA, DSP, IO & Peripherals
*Optimized PCB layout Gerber files downloadable from the Enpirion website to assure first pass design success.
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4/28/2009
Rev:B



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EP5382Q/EP5362Q/EP5352Q
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating
conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
PARAMETER
Input Supply Voltage
Voltages on: ENABLE, VSENSE, VS0-VS2
Voltage on: VFB
Storage Temperature Range
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
SYMBOL
VIN
TSTG
MIN
-0.3
-0.3
-0.3
-65
MAX
7.0
VIN + 0.3
2.7
150
260
2000
UNITS
V
V
V
°C
°C
V
Recommended Operating Conditions
PARAMETER
Input Voltage Range
Output Voltage Range
Operating Ambient Temperature
Operating Junction Temperature
SYMBOL
MIN
MAX
UNITS
VIN
VOUT
2.4 5.5
0.6 VIN-0.45
V
V
TA -40 +85 °C
TJ -40 +125 °C
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient (0 LFM)
Thermal Resistance: Junction to Case (0 LFM)
Thermal Shutdown
Thermal Shutdown Hysteresis
SYMBOL
θJA
θJC
TJ-TP
TYP
65
15
+150
15
UNITS
°C/W
°C/W
°C
°C
Electrical Characteristics
NOTE: TA = 25°C unless otherwise noted. Typical values are at VIN = 3.6V.
EP5352QI, EP5362QI: CIN = 2.2μF, COUT=10uF.
EP5382QI: CIN = 4.7μF, COUT=10uF.
PARAMETER
Operating Input Voltage
Under Voltage Lockout
UVLO Hysteresis
VOUT Initial Accuracy
VOUT Variation for all
Causes
SYMBOL
TEST CONDITIONS
VIN
VUVLO VIN going low to high
VOUT
VOUT
2.4V VIN 5.5V, ILOAD = 100mA;
TA = 25C
2.4V VIN 5.5V, ILOAD = 0 - 1A,
TA = -40°C to +85°C
Feedback Pin Voltage
Feedback Pin Input Current
VFB
IFB
Feedback Pin Voltage
VFB
Dynamic Voltage Slew Rate
Vslew
©Enpirion 2009 all rights reserved, E&OE
2.4V VIN 5.5V, ILOAD = 100mA
VSO=VS1=VS2=1
2.4V VIN 5.5V, ILOAD = 0-800mA,
TA = -40°C to +85°C
VSO=VS1=VS2=1
2
www.Dat0a3S1h32eet.in
4/28/2009
MIN
2.4
-2.0
-3.0
0.591
0.585
TYP
2.2
0.145
MAX
5.5
2.3
+2.0
+3.0
UNITS
V
V
V
%
%
0.603
1
0.603
0.615
0.621
V
nA
V
3 mV/μS
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PARAMETER
Continuous Output Current
EP5352QI
Continuous Output Current
EP5362QI
Continuous Output Current
EP5382QI
Shut-Down Current
Quiescent Current
PFET OCP Threshold
VS0-VS1 Voltage
Threshold
VS0-VS2 Pin Input Current
Enable Voltage Threshold
Enable Pin Input Current
Operating Frequency
PFET On Resistance
NFET On Resistance
Internal Inductor DCR
Soft-Start Operation
Time to 90% Vout
SYMBOL
TEST CONDITIONS
IOUT EP5352Q
IOUT EP5362Q
IOUT
ISD
ILIM
IVSX
IEN
FOSC
RDS(ON)
RDS(ON)
EP5382Q
Enable = Low
No switching
2.4V VIN 5.5V,
0.6V VOUT VIN – 0.6V
Pin = Low
Pin = High
Logic Low
Logic High
VIN = 3.6V
Tss Vout = 3.3V
EP5382Q/EP5362Q/EP5352Q
MIN TYP MAX UNITS
500 mA
600 mA
800 mA
0.75
800
μA
μA
1.4 2
A
0.0
1.4
0.4
VIN
V
1 nA
0.0
1.4
0.2
VIN
V
2 μA
4 MHz
340 mΩ
270 mΩ
.110 Ω
1 mS
©Enpirion 2009 all rights reserved, E&OE
www.Dat0a3S1h32eet.in
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4/28/2009
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Rev:B



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Pin Description
EP5382Q/EP5362Q/EP5352Q
VIN
VIN
GND
GND
VOUT
VOUT
1
2
3
4
5
6
16 VFB
15 VSENSE
14 NC
13 NC
12 NC
11 NC
VFB 16
VSENSE 15
NC 14
NC 13
NC 12
NC 11
Thermal
Pad
1 VIN
2 VIN
3 GND
4 GND
5 VOUT
6 VOUT
Figure 2. Pin description, top view.
VIN (Pin 1,2): Input voltage pin. Supplies power
to the IC. VIN can range from 2.4V to 5.5V.
Input GND: (Pin 3): Input power ground.
Connect this pin to the ground terminal of the
input capacitor.
Refer to
Layout
Recommendations for further details.
Output GND: (Pin 4): Power ground. The
output filter capacitor should be connected to
this pin. Refer to Layout recommendations for
further detail.
VOUT (Pin 5,6,7): Regulated output voltage.
NC (Pin 8,9,10,11,12,13,14): These pins
should not be electrically connected to each
other or to any external signal, voltage, or
ground. One or more of these pins may be
connected internally.
VSENSE (Pin 15): Sense pin for output voltage
regulation. Connect VSENSE to the output
voltage rail as close to the terminal of the
output filter capacitor as possible.
Figure 3. Pin description, bottom view.
VFB (Pin 16): Feed back pin for external divider
option. When using the external divider option
(VS0=VS1=VS2= high) connect this pin to the
center of the external divider. Set the divider
such that VFB = 0.603V.
VS0,VS1,VS2 (Pin 17,18,19): Output voltage
select. VS0=pin19, VS1=pin18, VS2=pin17.
Selects one of seven preset output voltages or
choose external divider by connecting pins to
logic high or low. Logic low is defined as VLOW
0.4V. Logic high is defined as VHIGH 1.4V.
Any level between these two values is
indeterminate. (refer to section on output
voltage select for more detail).
ENABLE (Pin 20): Output enable. Enable =
logic high, disable = logic low. Logic low is
defined as VLOW 0.2V. Logic high is defined
as VHIGH 1.4V. Any level between these two
values is indeterminate.
Thermal Pad. Thermal pad to remove heat
from package. Connect to surface ground pad
and PCB internal ground plane.
©Enpirion 2009 all rights reserved, E&OE
www.Dat0a3S1h32eet.in
4
4/28/2009
www.enpirion.com
Rev:B




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