EM48AM1684LBA Datasheet PDF - Eorex

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EM48AM1684LBA
Eorex

Part Number EM48AM1684LBA
Description 256Mb (4M x 4Bank x 16) Synchronous DRAM
Page 18 Pages


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Revision History
Revision 0.1 (Jul. 2006)
- First release.
Revision 0.2 (Mar. 2009)..
- Add “E” grade Part No.
EM48AM1684LBA
Mar. 2009
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EM48AM1684LBA
256Mb (4M×4Bank×16) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• VDD/VDDQ= 1.8V +/- 0.15V Power Supply
• LVCMOS Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms (7.8us)
Description
The EM48AM1684LBA is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
4Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 256Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 1.8V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVCMOS.
Available packages:
P-VFBGA 54B 12mm x 8mm x 1mm.
Ordering Information
Part No
EM48AM1684LBA-75F
EM48AM1684LBA-75FE
Organization
16M X 16
16M X 16
Max. Freq
133MHz @CL3
133MHz @CL3
Package
P-VFBGA -54B II
P-VFBGA -54B II
Grade Pb
Commercial Free
Extend temp. Free
Mar. 2009
* EOREX reserves the right to change products or specification without notice.
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Pin Assignment: TFBGA 54B
EM48AM1684LBA
1
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
A12
A8
VSS
2
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
3
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
7
A VDDQ
B VSSQ
C VDDQ
D VSSQ
E VDD
F /CAS
G BA0
H A0
J A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
/RAS
BA1
A1
A2
54ball P-VFBGA / (12mm × 8mm)
9
VDD
DQ1
DQ3
DQ5
DQ7
/WE
/CS
A10
VDD
Mar. 2009
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EM48AM1684LBA
Pin Description (Simplified)
Pin
F2
G9
F3
H7,H8,J8,J7,J3,
J2,H3,H2,H1,G3,
H9,G2,G1
G7,G8
F8
F7
F9
F1/E8
A8,B9,B8,C9,C8,
D9,D8,E9,E1,D2,
D1,C2,C1,B2,B1,
A2
A9,E7,J9/
A1,E3,J1
A7,B3,C7,D3/
A3,B7,C3,D7
E2
Name
CLK
/CS
CKE
A0~A12
BA0, BA1
/RAS
/CAS
/WE
UDQM/LDQM
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
Function
(System Clock)
Master clock input (Active on the positive rising edge)
(Chip Select)
Selects chip when active
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
CKE should be enabled at least one cycle prior to new
command. Disable input buffers for power down in standby.
(Address)
Row address (A0 to A12) is determined by A0 to A12 level at
the bank active command cycle CLK rising edge.
CA (CA0 to CA8) is determined by A0 to A8 level at the read or
write command cycle CLK rising edge.
And this column address becomes burst access start address.
A10 defines the pre-charge mode. When A10= High at the
pre-charge command cycle, all banks are pre-charged.
But when A10= Low at the pre-charge command cycle, only the
bank that is selected by BA0/BA1 is pre-charged.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK
with /RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the
CLK with /CAS low. Enables column access.
(Data Input/Output Mask)
DQM controls I/O buffers.
(Data Input/Output)
DQ pins have the same function as I/O pins on a conventional
DRAM.
(Power Supply/Ground)
VDD and VSS are power supply pins for internal circuits.
(Power Supply/Ground)
VDDQ and VSSQ are power supply pins for the output buffers.
(No Connection)
This pin is recommended to be left No Connection on the
device.
Mar. 2009
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EM48AM1684LBA datasheet pdf
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