EM428M1644RTA Datasheet PDF - Eorex

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EM428M1644RTA
Eorex

Part Number EM428M1644RTA
Description Double DATA RATE SDRAM
Page 20 Pages


EM428M1644RTA datasheet pdf
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EM428M1644RTA
128Mb (2M×4Bank×16)
Double DATA RATE SDRAM
Features
• Internal Double-Date-Rate architecture with 2
Accesses per clock cycle.
• VDD/VDDQ= 2.5V ±0.2V for (-75 and -6)
• VDD/VDDQ= 2.6V ±0.1V for (-5 )
• 2.5V SSTL-2 compatible I/O
• Burst Length (B/L) of 2, 4, 8
• 2,2.5,3 Clock read latency
• Bi-directional,intermittent data strobe(DQS)
• All inputs except data and DM are sampled
at the positive edge of the system clock.
• Data Mask (DM) for write data
• Sequential & Interleaved Burst type available
• Auto Precharge option for each burst accesses
• DQS edge-aligned with data for Read cycles
• DQS center-aligned with data for Write cycles
• DLL aligns DQ & DQS transitions with CLK’s
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms
Ordering Information
Description
The EM428M1644RTA is high speed Synchronous
graphic RAM fabricated with ultra high performance
CMOS process containing 134,217,728 bits which
organized as 2Meg words x 4 banks by 16 bits.
The 128Mb DDR SDRAM uses a double data rate
architecture to accomplish high-speed operation.
The data path internally prefetches multiple bits and
It transfers the datafor both rising and falling edges
of the system clock.It means the doubled data
bandwidth can be achieved at the I/O pins.
Available packages:TSOPII 66P 400mil.
Part No
EM428M1644RTA-75F
EM428M1644RTA-6F
EM428M1644RTA-5F
Organization Max. Freq
8M X 16
133MHz @CL2.5
8M X 16
166MHz @CL2.5
8M X 16
200MHz @CL3
EM 42 8M 16 4 4 R T A - X F E
Package
66pin TSOP(ll)
66pin TSOP(ll)
66pin TSOP(ll)
Grade
Commercial
Commercial
Commercial
Pb
Free
Free
Free
EOREX Memory
DDR SDRAM
Density
BM: 32 Mega
AM: 16 Mega
8M: 8 Mega
4M: 4 Mega
2M: 2 Mega
1M: 1 Mega
Organization
16: x16
Refresh
4: 4K
Bank
4: 4Bank
Grade
E: extended temp.
Package
F: Pb-free
Min Cycle Time (Max Freq.)
-5: 5ns (200MHz)
-6: 6ns (166MHz)
-75: 7.5ns (133MHz)
Revision
A: 1st
Package
T: TSOP
Interface
R: 2.5V
Apr. 2007
1/20
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EM428M1644RTA
* EOREX reserves the right to change products or specification without notice.
Apr. 2007
2/20
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Pin Assignment
EM428M1644RTA
66pin TSOP-II / (400mil × 875mil) / (0.65mm Pin pitch)
Apr. 2007
3/20
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EM428M1644RTA
Pin Description (Simplified)
Pin
45,46
24
44
28~32,35~41
26, 27
23
22
21
16/51
20/47
2, 4, 5, 7, 8, 10,
11, 13, 54, 56, 57,
59, 60, 62, 63, 65
1,18,33/
34,48,66
3, 9, 15, 55.61/
6, 12, 52, 58,64
14,17,19,25,42,
43,50,53
49
Name
CLK,/CLK
/CS
CKE
A0~A11
BA0, BA1
/RAS
/CAS
/WE
LDQS/UDQS
LDM/UDM
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC/RFU
VREF
Function
(System Clock)
Clock input active on the Positive rising edge except for DQ and
DM are active on both edge of the DQS.
CLK and /CLK are differential clock inputs.
(Chip Select)
/CS enables the command decoder when ”L” and disable the
command decoder when “H”.The new command are over-
Looked when the command decoder is disabled but previous
operation will still continue.
(Clock Enable)
Activates the CLK when “H” and deactivates when “L”.
When deactivate the clock,CKE low signifies the power down or
self refresh mode.
(Address)
Row address (A0 to A11) and Calumn address (CA0 to CA8) are
multiplexed on the same pin.
CA10 defines auto precharge at Calumn address.
(Bank Address)
Selects which bank is to be active.
(Row Address Strobe)
Latches Row Addresses on the positive rising edge of the CLK with
/RAS “L”. Enables row access & pre-charge.
(Column Address Strobe)
Latches Column Addresses on the positive rising edge of the CLK
with /CAS low. Enables column access.
(Write Enable)
Latches Column Addresses on the positive rising edge of the CLK
with /CAS low. Enables column access.
(Data Input/Output)
Data Inputs and Outputs are synchronized with both edge of DQS.
(Data Input/Output Mask)
DM controls data inputs.LDM corresponds to the data on
DQ0~DQ7.UDM corresponds to the data on DQ8~DQ15.
(Data Input/Output)
Data inputs and outputs are multiplexed on the same pin.
(Power Supply/Ground)
VDD and VSS are power supply pins for internal circuits.
(Power Supply/Ground)
VDDQ and VSSQ are power supply pins for the output buffers.
(No Connection/Reserved for Future Use)
This pin is recommended to be left No Connection on the device.
(Input)
SSTL-2 Reference voltage for input buffer.
Apr. 2007
4/20
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